Multichip IC devices with die embedded in glass substrate and a redistribution layer interconnect bridge
Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.
1 . An integrated circuit (IC) device, comprising:
a first IC die adjacent to a second IC die with a glass substrate therebetween, wherein each of the first and second IC dies further comprises a device layer over a die substrate and a plurality of conductive vias extending through the die substrate;
a first package routing structure on a first side of the first and second IC dies, the first package routing structure comprising a plurality of first metallization lines interconnecting each of the first and second IC dies to first-level package interconnect interfaces; and
a second package routing structure on a second side of the first and second IC dies, opposite the first side, the second package routing structure comprising a plurality of levels of second metallization lines electrically interconnecting the plurality of conductive vias of the first IC die to corresponding ones of the plurality of conductive vias of the second IC die.
2 . The IC device of claim 1 , further comprising one or more conductive through vias extending through the glass substrate and coupling one of the first metallization lines with one of the second metallization lines.
3 . The IC device of claim 1 , wherein each of the first and second metallization lines comprise predominantly Cu and the first and second package routing structures further comprise a polymer dielectric material surrounding each of the first and second metallization lines.
4 . The IC device of claim 3 , wherein the polymer dielectric material comprises epoxy, polyimide, or ABF.
5 . The IC device of claim 3 , wherein:
the polymer dielectric material is in direct contact with a first side of the glass substrate, and in direct contact with a second side of the glass substrate, opposite the first side of the glass substrate; and
the first package routing structure is in direct contact with the first or second IC die.
6 . The IC device of claim 1 , wherein the glass substrate is thicker than at least one of the first and second IC dies, and at least one of the first or second package routing structure is coupled to at least one of the first or second IC dies by a conductive through glass via.
7 . The IC device of claim 1 , further comprising first-level interconnect features in contact with the first-level interconnect interfaces, wherein the first-level interconnect features comprise a solder alloy.
8 . The IC device of claim 7 , further comprising a host component electrically coupled to the first-level interconnect interfaces through the first-level interconnect features.
9 . The IC device of claim 1 , wherein the first package routing structure and the second package routing structure consist of a same number of metallization levels.
10 . The IC device of claim 1 , wherein at least one of the levels of the second metallization lines comprises lines and spaces of less than 3 μm.
11 . A system comprising:
a plurality of laterally adjacent IC dies with a glass substrate material between edge sidewalls of the IC dies, wherein each of the IC dies further comprises a device layer over a die substrate and a plurality of conductive vias extending through the die substrate;
a first routing structure on a first side of the IC dies, the first routing structure comprising a plurality of first metallization lines embedded within a polymer dielectric material and interconnecting each of the IC dies to first-level interconnect features that are over the first side of the IC dies with the first routing structure therebetween; and
a second routing structure on a second side of the IC dies, the second routing structure comprising a plurality of levels of second metallization lines embedded within a polymer dielectric material and electrically interconnecting the plurality of conductive vias of a first of the IC dies to corresponding ones of the plurality of conductive vias of a second of the IC dies.
12 . The system of claim 11 , wherein:
the first and second metallization lines comprise predominantly Cu; and
the first routing structure and the second routing structure consist of a same number of metallization levels.
13 . The system of claim 11 , wherein:
the glass substrate material has a thickness substantially equal to a thickest one of the plurality of IC dies and thicker than a thinnest one of the plurality of IC dies; and
at least one of the first or second routing structure is coupled to the thinnest of the IC dies by a conductive through glass via.
14 . The system of claim 11 , further comprising:
a host component interconnected to the first routing structure through first-level interconnects coupled to the first-level interconnect features.
15 . The system of claim 11 , wherein at least one of the levels of the second metallization lines comprises lines and spaces of less than 3 μm.
16 . A method of fabricating an integrated circuit (IC) device, the method comprising:
placing a first IC die and a second IC die within one or more recesses in a glass substrate, wherein each of the IC dies further comprises a device layer over a die substrate and a plurality of conductive vias extending through the die substrate;
building up an organic dielectric material on opposite sides of the first and second IC dies and the glass substrate;
building up a plurality of levels of first and second interconnect lines within the organic dielectric material on opposite sides of the first and second IC dies and the glass substrate, wherein the plurality of levels of first interconnect lines are to electrically couple the first and second IC die to first level interconnect interfaces and wherein the plurality of levels of second interconnect lines electrically bridge the plurality of conductive vias of the first IC die to corresponding ones of the plurality of conductive vias of the second IC die.
17 . The method of claim 16 , further comprising:
forming a conductive through via through a portion of the glass substrate adjacent to at least one of the first or second IC dies; and
planarizing a surface of the glass substrate with at least one of the conductive through vias, first IC die or second IC die.
18 . The method of claim 16 , wherein building up the organic dielectric material comprises a dry film lamination or spin-on application process.
19 . The method of claim 16 , wherein at least one of the pluralit of levels of the second interconnect lines comprises lines and spaces of less than 3 μm.