IP Library › Granted Patent US 12696807
Granted Patent B2
US 12696807 · App. 18/089,459 · Granted Jul 28, 2026

Architectures for backside power delivery with stacked integrated circuit devices

Inventors: Suddhasattwa Nad (Chandler, AZ); Srinivas Pietambaram (Chandler, AZ); Brandon Marin (Gilbert, AZ); Jeremy Ecton (Gilbert, AZ); Gang Duan (Chandler, AZ)
Assignee: Intel Corporation
H10W90/00H10W72/823H10W80/312H10W80/327H10W90/288H10W90/291H10W90/792
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Quick Facts
Patent No.
US 12696807
App. No.
18/089,459
Granted
Jul 28, 2026
Kind
B2
Abstract

An apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. Other embodiments are also disclosed and claimed.

Claims (38)

1 . An apparatus comprising:

an integrated circuit logic device;

an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device;

one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device; and

conductive contacts on the second surface of the integrated circuit logic device.

2 . The apparatus of claim 1 , further comprising a glass frame adjacent the side of the integrated circuit logic device.

3 . The apparatus of claim 2 , wherein the glass frame further comprises channels through which liquid may flow.

4 . The apparatus of claim 2 , wherein the one more vias comprise through glass vias through the glass frame.

5 . The apparatus of claim 2 , wherein the glass frame is hybrid bonded with the integrated circuit power device.

6 . The apparatus of claim 1 , further comprising a copper slug adjacent the side of the integrated circuit logic device.

7 . The apparatus of claim 1 , further comprising mold material surrounding the one or more vias.

8 . The apparatus of claim 1 , further comprising an interposer coupled with the second surface of the integrated circuit logic device, wherein the interposer comprises an embedded integrated circuit device.

9 . The apparatus of claim 8 , wherein the embedded integrated circuit device comprises a device chosen from the group consisting of: high bandwidth memory (HBM), intelligent power device (IPD), photonic integrated circuit (PIC), and embedded passive components (EPC).

10 . The apparatus of claim 9 , wherein the interposer further comprises a first set of traces having a first diameter and a second set of traces having a second diameter, wherein the second diameter is greater than the first diameter and wherein the first traces are conductively coupled with the conductive contacts on the second surface of the integrated circuit logic device and wherein the second traces are conductively coupled with the one or more vias.

11 . A system comprising:

a host board;

an integrated circuit device package, the integrated circuit device package comprising:

an integrated circuit logic device;

an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device;

one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device;

conductive contacts on the second surface of the integrated circuit logic device; and

an interposer coupled with the second surface of the integrated circuit logic device; and

a power supply to provide power to the integrated circuit device package through the host board.

12 . The system of claim 11 , wherein the integrated circuit logic device is hybrid bonded with the integrated circuit power device.

13 . The system of claim 11 , wherein the interposer further comprises an embedded integrated circuit device comprising a device chosen from the group consisting of: high bandwidth memory (HBM), intelligent power device (IPD), photonic integrated circuit (PIC), and embedded passive components (EPC).

14 . The system of claim 11 , wherein the interposer further comprises a first set of traces having a first diameter and a second set of traces having a second diameter, wherein the second diameter is greater than the first diameter and wherein the first traces are conductively coupled with the conductive contacts on the second surface of the integrated circuit logic device and wherein the second traces are conductively coupled with the one or more vias.

15 . The system of claim 11 , further comprising a frame surrounding at least the side of the integrated circuit logic device, the frame adjacent at least the side of the integrated circuit logic device.

16 . A method comprising:

bonding a first surface of an integrated circuit logic device with an integrated circuit power device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device;

forming one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device;

applying mold material against the integrated circuit logic device; and

forming conductive contacts on the second surface of the integrated circuit logic device.

17 . The method of claim 16 , wherein forming one or more vias comprises placing a glass frame comprising the one or more vias adjacent the side of the integrated circuit logic device.

18 . The method of claim 16 , wherein forming one or more vias comprises:

drilling one or more openings in mold material over the integrated circuit power device; and

depositing metal in the openings.

19 . The method of claim 16 , further comprising coupling an interposer with the second surface of the integrated circuit logic device, wherein the interposer comprises an embedded integrated circuit device.

20 . The method of claim 16 , further comprising coupling a first set of interposer traces with the conductive contacts on the second surface of the integrated circuit logic device and coupling a second set of interposer traces with the one or more vias, wherein the first set of interposer traces have first diameter and the second set of interposer traces have a second diameter, wherein the second diameter is greater than the first diameter.