Carrier die with micro channel cooling and embedded components
A three-dimensional (3D) integrated circuit (IC) includes a plurality of dies, a carrier die, and a plurality of channels embedded in the carrier die. The plurality of dies is stacked in the 3D IC. Each of the dies includes circuitry. The carrier die is disposed above the stacked dies in the 3D IC. The carrier die is configured to provide mechanical support to the stacked dies in the 3D IC. The plurality of channels is configured to carry a coolant to cool the 3D IC.
1 . A three-dimensional (3D) integrated circuit (IC) comprising:
a plurality of dies stacked in the 3D IC, each of the stacked dies comprising circuitry;
a carrier die disposed above the stacked dies in the 3D IC, the carrier die configured to provide mechanical support to the stacked dies in the 3D IC, wherein the carrier die comprises one or more circuits connected to one or more of the stacked dies in the 3D IC by one or more vias in the carrier die and in the one or more of the stacked dies in the 3D IC; and
a plurality of channels embedded in the carrier die, the plurality of channels configured to carry a coolant to cool the 3D IC.
2 . The 3D IC of claim 1 wherein the plurality of channels is configured to carry a fluid coolant in a liquid or gaseous phase to remove heat from the stacked dies in the 3D IC.
3 . The 3D IC of claim 1 wherein the channels in the plurality of channels are unconnected to each other.
4 . The 3D IC of claim 1 wherein at least two of channels in the plurality of channels are connected to each other.
5 . The 3D IC of claim 1 wherein the channels in the plurality of channels are distributed evenly throughout the carrier die.
6 . The 3D IC of claim 1 wherein the channels in the plurality of channels are configured to provide a first cooling capacity at a first spatial region of the 3D IC and a second cooling capacity, different from the first cooling capacity, at a second spatial region of the 3D IC different from the first spatial region.
7 . The 3D IC of claim 1 wherein the channels in the plurality of channels are distributed in one or more different patterns in the carrier die.
8 . A system comprising the 3D IC of claim 1 and further comprising a coolant supply configured to supply the coolant to flow through the plurality of channels, the coolant configured to draw heat from the stacked dies in the 3D IC.
9 . The 3D IC of claim 1 wherein the one or more circuits comprise at least one of (i) passive electrical components, (ii) active electrical components, (iii) an amplifier, and (iv) a power regulator.
10 . The 3D IC of claim 9 wherein the passive electrical components comprise at least one of a resistor, a capacitor, and an inductor; and wherein the active electrical components comprise at least one of a transistor and a diode.
11 . The 3D IC of claim 1 wherein the channels in the plurality of channels in the carrier die are disposed around the one or more circuits in the carrier die.
12 . The 3D IC of claim 1 wherein the plurality of channels and the one or more circuits in the carrier die are disposed in a same plane.
13 . The 3D IC of claim 1 wherein the plurality of channels and the one or more circuits in the carrier die are disposed in different planes.
14 . The 3D IC of claim 1 further comprising a layer of silicon disposed around one of the stacked dies, wherein at least one of the one or more circuits is connected to the one or more of the stacked dies in the 3D IC by the one or more vias in the carrier die, the one or more of the stacked dies in the 3D IC, and the layer of silicon.
15 . An electronic system comprising the 3D IC of claim 1 and further comprising a printed circuit board (PCB) on which the 3D IC is mounted, wherein the PCB comprises at least one circuit connected to at least one of the one or more the circuits in the carrier die.
16 . The electronic system of claim 15 wherein the at least one circuit on the PCB is connected to the at least one of the one or more circuits in the carrier die by vias in the carrier die, the stacked dies in the 3D IC, and the PCB.
17 . The electronic system of claim 15 further comprising a layer of silicon disposed around one of the stacked dies, wherein the at least one circuit on the PCB is connected to the at least one of the one or more circuits in the carrier die by vias in the carrier die, the stacked dies in the 3D IC, the PCB, and the layer of silicon.
18 . The electronic system of claim 15 wherein:
the at least one circuit on the PCB comprises a first power regulator configured to regulate a first power supply configured to supply a first power to at least one of the stacked dies in the 3D IC; and
the at least one of the one or more circuits in the carrier die comprises a second power regulator configured to regulate a second power supply configured to supply a second power to at least one of the stacked dies in the 3D IC.
19 . The electronic system of claim 18 wherein the first and second power regulators are configured to regulate different voltages.
20 . A method of fabricating a three-dimensional (3D) integrated circuit (IC) comprising:
arranging a plurality of dies in a stack, each of the stacked dies comprising circuitry;
disposing a carrier die above the stacked dies to provide mechanical support to the stacked dies;
disposing one or more circuits in the carrier die;
connecting the one or more circuits to one or more of the stacked dies by one or more vias in the carrier die and in the one or more of the stacked dies;
embedding a plurality of channels in the carrier die; and
supplying a coolant through the plurality of channels to cool the 3D IC.
21 . The method of claim 20 further comprising embedding the plurality of channels in the carrier die by orthogonally disposing the plurality of channels in the carrier die using at least one of drilling and etching processes.
22 . The method of claim 20 further comprising providing a first cooling capacity at a first spatial region of the 3D IC and a second cooling capacity, different from the first cooling capacity, at a second spatial region of the 3D IC different from the first spatial region.
23 . The method of claim 20 further comprising arranging the plurality of channels and the one or more circuits in the carrier die in respective planes.
24 . The method of claim 20 further comprising disposing the plurality of channels in the carrier die around the one or more circuits in the carrier die.
25 . The method of claim 20 further comprising:
disposing a layer of silicon disposed around one of the stacked dies; and
connecting at least one of the one or more circuits to one or more of the stacked dies by the one or more vias in the carrier die, the one or more of the stacked dies in the 3D IC, and the layer of silicon.
26 . The method of claim 20 further comprising:
mounting the 3D IC on a printed circuit board (PCB) comprising at least one circuit; and
connecting the at least one circuit on the PCB to at least one of the one or more circuits in the carrier die.
27 . The method of claim 26 further comprising:
disposing a layer of silicon around one of the stacked dies; and
connecting the at least one circuit on the PCB to at least one of the one or more circuits in the carrier die by vias in the carrier die, the stacked dies in the 3D IC, the PCB, and the layer of silicon.
28 . The method of claim 26 further comprising:
regulating a first power supply configured to supply a first power to at least one of the stacked dies using a first power regulator disposed in the at least one circuit on the PCB; and
regulating a second power supply configured to supply a second power to at least one of the stacked dies using a second power regulator disposed in at least one of the one or more circuits in the carrier die.