Heterogeneous annealing method and device
A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provide a bonded structure with reliable electrical contacts.
1 . A bonded structure comprising:
a first element having a first surface with a first insulating region and a first contact structure, the first element comprising a first semiconductor substrate, the first element having a thickness less than 100 microns;
a second element having a second surface with a second insulating region and a second contact structure, the second element comprising a second semiconductor substrate, wherein the second insulating region and the second contact structure are disposed over the second semiconductor substrate, wherein the first insulating region is directly bonded to the second insulating region and the first contact structure is directly bonded to the second contact structure such that the first and second elements are directly bonded in a face-to-face arrangement; and
a third semiconductor element consisting of a silicon base and a bonding layer, the bonding layer of the third semiconductor element directly bonded to a second surface of the first element, the second surface opposite the first surface, wherein the third semiconductor element has a thickness greater than the thickness of the first element and wherein a difference in coefficient of thermal expansion (CTE) between the silicon base of the third semiconductor element and the second semiconductor substrate of the second element is less than 1.0 ppm/° C.
2 . The bonded structure of claim 1 , wherein the thickness of the third semiconductor element is between about 0.5 mm-0.8 mm.
3 . The bonded structure of claim 1 , wherein the CTE difference is less than 0.5 ppm/° C.
4 . The bonded structure of claim 3 , wherein the CTE difference is less than 0.3 ppm/° C.
5 . The bonded structure of claim 3 , wherein a CTE difference between the first semiconductor substrate of the first element and the second semiconductor substrate of the second element is in a range of 2 ppm/° C. to 5 ppm/° C.
6 . The bonded structure of claim 1 , wherein at least one of the first element and the second element has a conductive via extending at least partially therethrough and electrically connected to the contact structures.
7 . The bonded structure of claim 6 , wherein each of the first element and the second element has a plurality of conductive vias, and the conductive vias of the first element are aligned with the conductive vias of the second element.
8 . The bonded structure of claim 6 , wherein the conductive via extends through most or all of the thickness of the at least one of the first element and the second element.
9 . The bonded structure of claim 1 , wherein at least one of the first and second insulating regions comprises silicon oxide.
10 . The bonded structure of claim 1 , wherein the second semiconductor substrate of the second element comprises a silicon substrate.
11 . A bonded structure comprising:
a first element comprising a first semiconductor material with a front side and a back side opposite the front side, the first semiconductor material including a first device layer at the front side of the first semiconductor material, the first element further comprising a first surface, the first surface having a first insulating region and a first contact structure, the first insulating region and the first contact structure disposed on the front side of the first semiconductor material, the first element having a thickness less than 100 microns;
a second element comprising a second semiconductor material and a second surface, the second surface having a second insulating region and a second contact structure, wherein the first insulating region is directly bonded to the second insulating region and the first contact structure is directly bonded to the second contact structure; and
a third element directly bonded to the first element, wherein the third element has a thickness greater than the thickness of the first element, wherein the third element comprises a third semiconductor material and wherein a difference in coefficient of thermal expansion (CTE) between the third semiconductor material and the second semiconductor material is less than 1.0 ppm/° C.,
wherein the first element is vertically between the second element and the third element,
wherein the first and second contact structures form a part of an electronic circuit, and the electronic circuit does not extend into the third element.
12 . The bonded structure of claim 11 , wherein the third element consists of the third semiconductor material and a bonding layer, the bonding layer directly bonded to the first element, the third semiconductor material comprising a silicon base.
13 . The bonded structure of claim 11 , wherein the thickness of the third element is between about 0.5 mm-0.8 mm.
14 . The bonded structure of claim 11 , wherein the CTE difference is less than 0.5 ppm/° C.
15 . The bonded structure of claim 14 , wherein a CTE difference between the first semiconductor material of the first element and the second semiconductor material of the second element is in a range of 2 ppm/° C. to 5 ppm/° C.
16 . The bonded structure of claim 11 , wherein at least one of the first element and the second element has a conductive via extending at least partially therethrough and electrically connected to the contact structures.
17 . The bonded structure of claim 16 , wherein each of the first element and the second element has a plurality of conductive vias, and the conductive vias of the first element are aligned with the conductive vias of the second element.
18 . The bonded structure of claim 16 , wherein the conductive via extends through most or all of the thickness of the at least one of the first element and the second element.
19 . The bonded structure of claim 11 , wherein at least one of the first and second insulating regions comprises silicon oxide.
20 . The bonded structure of claim 11 , wherein the second semiconductor material of the second element comprises silicon.
21 . The bonded structure of claim 11 , wherein the third semiconductor material of the third element comprises silicon.
22 . The bonded structure of claim 11 , wherein the first element comprises first integrated circuits (ICs) and the second element comprises second ICs, the first ICs and the second ICs having different sizes.
23 . The bonded structure of claim 11 , further comprising a first integrated circuit (IC) having a digital function and a second IC having an optical function.
24 . The bonded structure of claim 23 , wherein the first element comprises the first IC and the second element comprises the second IC.
25 . The bonded structure of claim 11 , wherein the third element serves as a packaging structure to support the bonded structure.
26 . The bonded structure of claim 11 , wherein the third element does not have any circuits.
27 . The bonded structure of claim 26 , wherein the first element comprises integrated circuits (ICs).
28 . A bonded structure comprising:
a first element comprising a first semiconductor layer and a first surface below the first semiconductor layer, wherein the first semiconductor layer includes one or more devices at a lower side of the first semiconductor layer, wherein the first surface has a first insulating region and a first contact structure, and wherein the first element has a thickness less than 100 microns;
a second element comprising a second semiconductor layer and a second surface, the second surface having a second insulating region and a second contact structure, wherein the second element is disposed below the first element, and wherein the first insulating region is directly bonded to and in contact with the second insulating region and the first contact structure is directly bonded to the second contact structure; and
a third element directly bonded to the first element, wherein the third element is disposed above the first element, wherein the third element has a thickness greater than the thickness of the first element, wherein the third element comprises a third semiconductor layer and wherein a difference in coefficient of thermal expansion (CTE) between the third semiconductor layer and the second semiconductor layer is less than 1.0 ppm/° C.,
wherein the third semiconductor element does not have any electronic circuits.
29 . The bonded structure of claim 28 , wherein the third element consists of the third semiconductor layer and a bonding layer, the bonding layer directly bonded to the first element, the third semiconductor layer comprising silicon.
30 . The bonded structure of claim 29 , wherein the second semiconductor layer of the second element comprises silicon.
31 . The bonded structure of claim 28 , wherein the first element comprises first integrated circuits (ICs) and the second element comprises second ICs, the first ICs and the second ICs having different sizes.
32 . The bonded structure of claim 28 , further comprising a first integrated circuit (IC) having a digital function and a second IC having an optical function.
33 . The bonded structure of claim 32 , wherein the first element comprises the first IC and the second element comprises the second IC.