Semiconductor device manufacturing apparatus and manufacturing method
A semiconductor device manufacturing device comprises: a stage; two bonding heads which are mutually independently horizontally movable; and a controller for causing each of the two bonding heads to perform a positioning process for horizontal positioning, a grounding process for lowering the chip until the chip is grounded on a substrate, and a pressurizing process for applying a bonding load to the chip that is grounded. The controller causes the two bonding heads to perform the positioning process and the grounding process independently from each other in a non-pressurizing period in which neither of the bonding heads is performing the pressurizing process, and causes the two bonding heads after completing the positioning process and the grounding process to perform the pressurizing process in parallel.
1 . A semiconductor device manufacturing method for manufacturing a semiconductor device by bonding a chip to a substrate placed on a stage, comprising:
executing, by each of a plurality of bonding heads movable in a horizontal direction independently of each other and each having a bonding tool holding a chip and movable in a vertical direction, a positioning step for horizontal positioning, a grounding step for lowering the chip until the chip is grounded to the substrate or another chip, and a pressurizing step for applying a bonding load to the chip that is grounded;
executing, by the plurality of bonding heads, the positioning step and the grounding step independently of each other during a non-pressurizing period in which none of the bonding heads is executing the pressurizing step;
providing, by a controller, a predetermined stand-by time set in advance based on a difference of end timings of the grounding steps among the plurality of bonding heads;
executing, by at least two bonding heads that have completed the positioning step and the grounding step, the pressurizing step in parallel so that their execution periods at least partially overlap; and
staggering execution timings of receiving processes so that execution times of the receiving processes for receiving new chips by the plurality of bonding heads do not overlap each other.