Crossovers for vacuum packaging
In some embodiments, electromechanical systems including a semiconductor layer that has a planar surface and includes conductive and adjacent non-conductive regions and a hermetic seal applied above the planar surface and methods of manufacturing the systems are disclosed. In some embodiments, electromechanical devices that include first and second planar semiconductor layers are disclosed. Each of the semiconductor layers includes conductive regions, and at least one conductive region from each of the layers is electrically coupled to each other. Methods of manufacturing the electromechanical devices are also disclosed.
1 . A method for manufacturing electromechanical systems, comprising:
providing a semiconductor layer having a planar surface;
forming conductive regions and adjacent non-conductive regions in the semiconductor layer by modifying a composition of the semiconductor layer,
wherein the planar surface comprises surfaces of the conductive regions and the non-conductive regions;
applying a hermetic seal above the planar surface to create a hermetically sealed volume, wherein:
a conductive region of the conductive regions comprises a first part disposed below the hermetically sealed volume and a second part disposed outside the hermetically sealed volume; and
oxidizing the non-conductive regions, wherein:
the oxidizing is performed after formation of the conductive regions;
the oxidizing selectively converts the non-conductive regions into an electrically insulating oxide;
the electrically insulating oxide is retained to electrically isolate adjacent conductive regions; and
the oxidizing is not performed for dopant diffusion or dopant drive-in.
2 . The method of claim 1 , wherein forming the conductive regions in the semiconductor layer comprises doping regions of the semiconductor layer to form conductive regions.
3 . The method of claim 2 , wherein doping the regions of the semiconductor layer further comprises N-type doping of the regions.
4 . The method of claim 2 , further comprising P-type doping of the regions of the semiconductor layer to form the non-conductive regions.
5 . The method of claim 1 , wherein the hermetically sealed volume is a vacuum.
6 . The method of claim 1 , wherein the conductive regions are formed without changing a topography of the semiconductor layer.
7 . The method of claim 1 , wherein forming the conductive regions in the semiconductor layer comprises forming a silicide in regions of the semiconductor layer.
8 . The method of claim 7 , wherein forming the silicide further comprises depositing patterned metal on top of the semiconductor layer.
9 . The method of claim 1 , wherein a surface of the semiconductor layer spans dimensions greater than 620 mm by 750 mm.
10 . The method of claim 1 , wherein the non-conductive regions in the semiconductor layer comprise undoped semiconductor.
11 . The method of claim 1 , wherein the conductive regions are formed without removing material from the semiconductor layer.
12 . The method of claim 1 , further comprising electrically coupling a via to the conductive region.
13 . The method of claim 1 , further comprising electrically coupling the conductive region to a bolometer circuit.
14 . The method of claim 1 , wherein providing a semiconductor layer having the planar surface comprises depositing the semiconductor layer on a glass substrate.
15 . The method of claim 1 , further comprising providing an insulating layer above the semiconductor layer and below the hermetic seal.
16 . The method of claim 1 , further comprising separating the semiconductor layer into a plurality of separated portions, wherein applying the hermetic seal further comprises applying the hermetic seal on top of a separated portion.
17 . The method of claim 1 , wherein oxidizing the non-conductive regions comprises:
forming an oxide layer on the non-conductive regions of the semiconductor layer while inhibiting oxidation of the conductive regions;
wherein the oxide layer is retained between adjacent conductive regions beneath the hermetic seal to provide electrical isolation; and
wherein oxide formed outside the hermetically sealed volume is removed prior to completion of the hermetic seal.