IP Library Granted Patent US 12699003
Granted Patent B2
US 12699003 · App. 18/139,241 · Granted Aug 4, 2026

Method and apparatus for interference reduction in optical sensing receivers

Inventors: Junjie Lu (Irvine, CA); Jing Guo (Irvine, CA); Leon Samuel Wang (Irvine, CA); Xiaofeng Lin (Irvine, CA); Xicheng Jiang (Irvine, CA)
Assignee: Avago Technologies International Sales Pte. Limited
G01J1/44H03H11/04G01J2001/444
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Quick Facts
Patent No.
US 12699003
App. No.
18/139,241
Granted
Aug 4, 2026
Kind
B2
Abstract

An apparatus includes a first circuit that has a photodetector. The photodetector is reverse-biased by a reverse-bias voltage. A common mode voltage is added to the reverse-bias voltage to provide an offset to the photodetector voltage. A second circuit is coupled to the first circuit to provide the common mode voltage for the first circuit. A third circuit is coupled to the second circuit that includes a first voltage source and a second voltage source having opposite voltages equal to half of the reverse-bias voltage. Each one of the first voltage source and the second voltage source are coupled between separate input and output nodes of input and output ports of the third circuit. The first voltage source and the second voltage source provide the reverse-bias voltage to the first circuit to reverse-bias the photodetector. The third circuit provides a photodetector current at an output of the third circuit.

Claims (45)

1 . An apparatus comprising:

a photodetector, wherein the photodetector is reverse-biased by a reverse-bias voltage (V PD ), and wherein a first voltage provided to an anode of the photodetector and a second voltage provided to a cathode of the photodetector are generated based on a common mode voltage (V o ) and the reverse-bias voltage;

a first circuit coupled to the anode and the cathode of the photodetector and configured to provide the common mode voltage to both the anode and the cathode of the photodetector, wherein the first voltage provided to the anode is offset by a negative amount of V PD and the second voltage provided to the cathode is offset by a positive amount of V PD ; and

a second circuit coupled to the first circuit that comprises a first voltage source and a second voltage source and configured to provide the reverse-bias voltage for the photodetector, wherein each one of the first voltage source and the second voltage source are coupled to one of the anode or the cathode of the photodetector, wherein the second circuit is configured to receive a current of the photodetector via the first circuit and to provide the current of the photodetector at an output of the second circuit.

2 . The apparatus of claim 1 , wherein the first circuit comprises a third voltage source configured to generate the common mode voltage.

3 . The apparatus of claim 2 , wherein the first circuit comprises:

an operational-amplifier (Op-Amp), wherein an inverting node of the Op-Amp is coupled to a first node between first and second capacitors of the first circuit, an output node of the Op-Amp is coupled to a second node between third and fourth capacitors of the first circuit, and the third voltage source is coupled between a non-inverting node of the Op-Amp and a ground to provide the common mode voltage to the non-inverting node of the Op-Amp.

4 . The apparatus of claim 1 , further comprising:

a third circuit that comprises a low noise amplifier is coupled to the second circuit and is configured to amplify the current of the photodetector, received from the photodetector via the first circuit and the second circuit and provide an output voltage proportional to the current of the photodetector.

5 . The apparatus of claim 4 , wherein the first, second, and third circuits provide differential signal paths.

6 . The apparatus of claim 1 , wherein the second circuit is configured to provide the reverse-bias voltage, via the first circuit to the photodetector, and wherein the second circuit is configured to receive the current of the photodetector via the first circuit.

7 . The apparatus of claim 1 , wherein voltages at the cathode and the anode of the photodetector are set at V o +½V PD and V o −½V PD respectively.

8 . An apparatus comprising:

a first circuit comprising a first port, a second port, and a third voltage source configured to provide a common mode voltage (V o ), the first circuit is configured to:

receive a current at the first port,

receive a first bias voltage at a first node of the second port and a second bias voltage having an opposite polarity of the first bias voltage at a second node of the second port, wherein the common mode voltage is added to the first and second bias voltages as an offset, and

provide the first bias voltage plus the common mode voltage at a first node of the first port and the second bias voltage plus the common mode voltage at a second node of the first port; and

a second circuit, coupled to the second port of the first circuit, the second circuit that comprises a first voltage source configured to provide the first bias voltage and a second voltage source configured to provide the second bias voltage, wherein each one of the first voltage source and the second voltage source are coupled between separate input and output nodes of input and output ports of the second circuit.

9 . The apparatus of claim 8 , wherein the second circuit is configured to receive the current from the first circuit and to provide the current, the apparatus further comprising:

a third circuit coupled to the second circuit and configured to receive the current, amplify the current, and provide an output voltage proportional to the current.

10 . The apparatus of claim 9 , wherein the first, second, and third circuits provide fully differential signal paths.

11 . The apparatus of claim 8 , further comprising:

a photodetector coupled to the first port, wherein the first bias voltage plus the common mode voltage and the second bias voltage plus the common mode voltage are applied to a cathode and an anode of the photodetector to reverse-bias the photodetector by a sum of magnitudes of the first and second bias voltages (V PD ).

12 . The apparatus of claim 11 , wherein the first bias voltage plus the common mode voltage is presented as V o +½V PD that is applied to the cathode of the photodetector, and wherein the second bias voltage plus the common mode voltage is presented as V o −½V PD that is applied to the cathode of the photodetector.

13 . The apparatus of claim 12 , wherein the photodetector is reverse-biased by the sum of the magnitudes of the first and second bias voltages.

14 . The apparatus of claim 9 , wherein the first circuit is configured to filter an electromagnetic interference, received by the first and second nodes of the first port, and prevent the electromagnetic interference, outside a frequency band of the current, from reaching the third circuit.

15 . An apparatus comprising:

a first circuit that comprises a photodetector;

a second circuit coupled to the first circuit and comprising a first voltage source that provides a common mode voltage (V o ); and

a third circuit coupled the second circuit that comprises a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor are configured to be charged to a first voltage (V 1 ) based on a current source provided to the third circuit and a first feedback resistor and a second voltage (V 2 ) based on the current source and a second feedback resistor, wherein the first capacitor and the second capacitor are configured to provide the first voltage and the second voltage to the first circuit to be coupled to an anode and a cathode of the photodetector to reverse-bias the photodetector, and wherein the common mode voltage is applied to both the anode and the cathode of the photodetector.

16 . The apparatus of claim 15 , wherein:

the photodetector is reverse-biased by a sum (V PD ) of magnitudes of the first and second voltages,

bias voltages at the cathode and the anode of the photodetector are set to V o +½V PD and V o −½V PD respectively,

voltages at first and second nodes of a first interface between the third circuit and the second circuit are set to V o +½V PD and V o −½V PD respectively, and

voltages at the first and second nodes of a second interface between the second circuit and the first circuit are set to V o +½V PD and V o −½V PD , respectively.

17 . The apparatus of claim 15 , further comprising:

a fourth circuit coupled to the third circuit and configured to amplify a current of the photodetector, received via the second circuit and the third circuit, and provide an output voltage proportional to the current of the photodetector.

18 . The apparatus of claim 17 , wherein the second circuit is configured to filter an electromagnetic interference, received by the first circuit, and prevent the electromagnetic interference from reaching the fourth circuit.

19 . The apparatus of claim 15 , wherein the third circuit further comprises:

first and second variable resistors;

first and second operational-amplifiers (Op-Amps);

third and fourth resistors, wherein each one of the third and fourth resistors is coupled between an inverting node and output node of one of the first and second Op-Amps; and

a current source configured to charge the first capacitor and the second capacitor,

wherein the first and second variable resistors are used to adjust time constants of charging the first capacitor and the second capacitor.

20 . The apparatus of claim 19 , wherein the first and the second variable resistors are implemented by metal oxide semiconductor field effect transistors in weak inversion region to increase resistances of the first and the second variable resistors and to reduce thermal noise.