Semiconductor test key structure and test method of semiconductor structure
The invention provides a semiconductor test key structure, which comprises a substrate, a plurality of gate structures located on the substrate, a plurality of thin film resistor layers, wherein each thin film resistor layer is located above one of the gate structures, and the thin film resistor layers are located in a dielectric layer, a test key circuit layer is located on the dielectric layer, wherein the test key circuit layer is a square wave pattern from a top view, and two contact pads are respectively connected with the test key circuit layer.
1 . A semiconductor test key structure, characterized in that:
a substrate;
a plurality of gate structures located on the substrate;
a plurality of thin film resistor layers, wherein each thin film resistor layer is vertically overlapping with one of the gate structures, and the thin film resistor layers are located in a dielectric layer;
a test key circuit layer located on the dielectric layer, wherein the test key circuit layer is a square wave pattern when viewed from a top view, wherein the square wave pattern comprises a plurality of strip patterns and a plurality of connection patterns, wherein each strip pattern is arranged along a first direction and each connection pattern is arranged along a second direction, and each connection pattern is connected in series with a respective head end of two adjacent strip patterns or a respective tail end of two adjacent strip patterns, so that the plurality of strip patterns and the plurality of connection patterns form a continuous square wave pattern; and
two contact pads, which are respectively connected with two ends of the test key circuit layer.
2 . The semiconductor test key structure according to claim 1 , wherein a distance from a bottom surface of the test key circuit layer to a top surface of any one of the plurality of thin film resistor layers is less than 500 angstroms along a vertical direction.
3 . The semiconductor test key structure according to claim 1 , wherein only the dielectric layer is included between the test key circuit layer and any thin film resistor layer along a vertical direction, and no other elements are included between the test key circuit layer and any thin film resistor layer.
4 . The semiconductor test key structure according to claim 1 , wherein the distance between a right side of any one of the strip patterns and a right side of another adjacent strip pattern of the strip patterns in the second direction is greater than 100 nm.
5 . The semiconductor test key structure according to claim 1 , wherein any one of the plurality of thin film resistor layers is rectangular when viewed from a top view, and a long side along the first direction is greater than 640 nm, and a short side along the second direction is greater than 100 nm.
6 . The semiconductor test key structure according to claim 1 , wherein a low voltage device region, a medium voltage device region and a high voltage device region are defined on the substrate, and the plurality of gate structures include a low voltage gate structure located in the low voltage device region, a medium voltage gate structure located in the medium voltage device region, and a high voltage gate structure located in the high voltage device region.
7 . The semiconductor test key structure according to claim 6 , wherein the thin film resistor layers include a low voltage thin film resistor layer located on the low voltage gate structure, a medium voltage thin film resistor layer located on the medium voltage gate structure, and a high voltage thin film resistor layer located on the high voltage gate structure.
8 . The semiconductor test key structure according to claim 6 , wherein the test key circuit layer spans the low voltage device region, the medium voltage device region and the high voltage device region.
9 . A method for testing a semiconductor structure, characterized in that:
providing a substrate;
forming a plurality of gate structures on the substrate;
forming a plurality of thin film resistor layers, wherein each thin film resistor layer is vertically overlapping with one of the gate structures, and the thin film resistor layers are positioned in a dielectric layer;
forming a test key circuit layer on the dielectric layer, wherein the test key circuit layer is a square wave pattern when viewed from a top view, wherein the square wave pattern comprises a plurality of strip patterns and a plurality of connection patterns, wherein each strip pattern is arranged along a first direction and each connection pattern is arranged along a second direction, and each connection pattern is connected in series with a respective head end of two adjacent strip patterns or a respective tail end of two adjacent strip patterns, so that the plurality of strip patterns and the plurality of connection patterns form a continuous square wave pattern;
forming two contact pads which are respectively connected with two ends of the test key circuit layer;
applying a voltage to the two contact pads and gradually increasing the voltage; and
observing whether any one of the plurality of thin film resistor layers exhibits an increase in resistance representing an open circuit condition.
10 . The test method of semiconductor structure according to claim 9 , wherein a distance from a bottom surface of the test key circuit layer to a top surface of any one of the plurality of thin film resistor layer is less than 500 angstroms along a vertical direction.
11 . The test method of semiconductor structure according to claim 9 , wherein only the dielectric layer is included between the test key circuit layer and any thin film resistor layer along a vertical direction, and no other elements are included between the test key circuit layer and any thin film resistor layer.
12 . The method for testing a semiconductor structure according to claim 9 , wherein the distance between a right side of any one of the strip patterns and a right side of another adjacent strip pattern in the second direction is greater than 100 nm.
13 . The method for testing a semiconductor structure according to claim 9 , wherein when viewed from a top view, any one of the plurality of thin film resistor layers is rectangular, and a long side along the first direction is greater than 640 nm, and a short side along the second direction is greater than 100 nm.
14 . The test method of semiconductor structure according to claim 9 , wherein a low voltage device region, a medium voltage device region and a high voltage device region are defined on the substrate, and the plurality of gate structures include a low voltage gate structure located in the low voltage device region, a medium voltage gate structure located in the medium voltage device region and a high voltage gate structure located in the high voltage device region.
15 . The test method of semiconductor structure according to claim 14 , wherein the plurality of thin film resistor layers comprise a low voltage thin film resistor layer located on the low voltage gate structure, a medium voltage thin film resistor layer located on the medium voltage gate structure, and a high voltage thin film resistor layer located on the high voltage gate structure.
16 . The method for testing a semiconductor structure according to claim 14 , wherein the test key circuit layer spans the low voltage device region, the medium voltage device region and the high voltage device region.