Flexible test instruction set architecture
Techniques for the testing of devices are disclosed. A testing environment is accessed. The testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM. A device under test (DUT) is accessible by the command interface. The testing environment includes a test instruction set architecture (TISA). A test sequence is programmed by a user. The test sequence includes one or more instructions from within the TISA. The test sequence is stored in the instruction RAM. A first instruction is fetched by the FAD. The fetching includes decoding the first instruction. The first instruction is translated by the code exerciser. The translating produces a first packetized communication, which is sent to the DUT. A first packetized response is received by the command interface from the DUT and is reported to the user.
1 . A processor-implemented method for testing comprising:
accessing a testing environment, wherein the testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM, wherein a device under test (DUT) is accessible by the command interface, and wherein the testing environment includes a test instruction set architecture (TISA), wherein the TISA includes a plurality of opcodes, wherein the plurality of opcodes configure the testing environment;
programming a test sequence, by a user, wherein the test sequence includes one or more instructions from within the TISA;
storing, in the instruction RAM, the test sequence that was programmed;
fetching, by the FAD, a first instruction from the test sequence that was stored in the instruction RAM, wherein the fetching includes decoding the first instruction;
translating, by the code exerciser, the first instruction, wherein the translating produces a first packetized communication, wherein the DUT is responsive to the first packetized communication;
sending the first packetized communication, by the command interface, to the DUT;
receiving a first packetized response, by the command interface, from the DUT, wherein the first packetized response is stored in a trace RAM; and
reporting, to the user, the first packetized response that was stored in the trace RAM.
2 . The method of claim 1 further comprising initializing the testing environment, wherein the initializing includes control instructions in the TISA.
3 . The method of claim 1 wherein the TISA includes a first grouping of opcodes, wherein the first grouping of opcodes controls the testing environment.
4 . The method of claim 3 wherein the TISA includes a second grouping of opcodes, wherein the second grouping of opcodes exercises the DUT.
5 . The method of claim 1 further comprising adding, to the TISA, one or more new instructions, wherein the one or more new instructions exercise a second DUT.
6 . The method of claim 1 wherein the TISA comprises one or more data words.
7 . The method of claim 6 wherein a first data word within the one or more data words comprises 32 bits.
8 . The method of claim 7 wherein the first data word includes an opcode field, wherein the opcode field comprises 5 bits.
9 . The method of claim 8 wherein the first data word includes a first argument field, wherein the first argument field comprises 4 bits.
10 . The method of claim 9 wherein the first data word includes a second argument field, and wherein the second argument field comprises 10 bits.
11 . The method of claim 10 wherein the first data word includes a third argument field, and wherein the third argument field comprises 4 bits.
12 . The method of claim 11 wherein the first data word includes a fourth argument field, and wherein the third argument field comprises 9 bits.
13 . The method of claim 6 wherein a second data word comprises 32 bits, and wherein the second data word includes a first data pattern or a start address.
14 . The method of claim 6 wherein a third data word comprises 32 bits, and wherein the third data word includes a second data pattern.
15 . The method of claim 1 wherein the receiving includes a second packetized response.
16 . The method of claim 1 wherein the fetching and translating include a second instruction.
17 . The method of claim 16 wherein the sending includes a second packetized communication.
18 . The method of claim 1 wherein the DUT comprises a PCIExpress (PCIe) controller.
19 . The method of claim 18 wherein the sending comprises simulated traffic from a PCIe root complex.
20 . The method of claim 18 wherein the sending comprises simulated traffic from a PCIe endpoint.
21 . The method of claim 1 wherein the DUT comprises a compute express link (CXL) controller.
22 . The method of claim 1 wherein the DUT comprises an ethernet controller.
23 . The method of claim 1 wherein the TISA includes a plurality of opcodes.
24 . The method of claim 23 further comprising launching, by one or more opcodes within the plurality of opcodes, a compliance test on the DUT, by the testing environment.
25 . The method of claim 24 wherein the compliance test includes a PCIe compliance test suite (CTS).
26 . A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to perform operations of:
accessing a testing environment, wherein the testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM, wherein a device under test (DUT) is accessible by the command interface, and wherein the testing environment includes a test instruction set architecture (TISA), wherein the TISA includes a plurality of opcodes, wherein the plurality of opcodes configure the testing environment;
programming a test sequence, by a user, wherein the test sequence includes one or more instructions from within the TISA;
storing, in the instruction RAM, the test sequence that was programmed;
fetching, by the FAD, a first instruction from the test sequence that was stored in the instruction RAM, wherein the fetching includes decoding the first instruction;
translating, by the code exerciser, the first instruction, wherein the translating produces a first packetized communication, wherein the DUT is responsive to the first packetized communication;
sending the first packetized communication, by the command interface, to the DUT;
receiving a first packetized response, by the command interface, from the DUT, wherein the first packetized response is stored in a trace RAM; and
reporting, to the user, the first packetized response that was stored in the trace RAM.
27 . A computer system for instruction execution comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
access a testing environment, wherein the testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM, wherein a device under test (DUT) is accessible by the command interface, and wherein the testing environment includes a test instruction set architecture (TISA), wherein the TISA includes a plurality of opcodes, wherein the plurality of opcodes configure the testing environment;
program a test sequence, by a user, wherein the test sequence includes one or more instructions from within the TISA;
store, in the instruction RAM, the test sequence that was programmed;
fetch, by the FAD, a first instruction from the test sequence that was stored in the instruction RAM, wherein the fetching includes decoding the first instruction;
translate, by the code exerciser, the first instruction, wherein the translating produces a first packetized communication, wherein the DUT is responsive to the first packetized communication;
send the first packetized communication, by the command interface, to the DUT;
receive a first packetized response, by the command interface, from the DUT, wherein the first packetized response is stored in a trace RAM; and
report, to the user, the first packetized response that was stored in the trace RAM.