Built-in self-test for on-chip error detection
The present disclosure generally relates to using built-in self-test (BIST) for on-chip error detection. In some aspects, a method includes receiving information about one or more parameters for a built-in self-test (BIST) operation, generating a nonce for each iteration of the BIST operation according to the one or more parameters, and computing a hash value for each iteration of the BIST operation using the nonce as an input to a cryptographic hash function. The method further includes transmitting, to multiple hash engines, information about the nonce and the hash value for each iteration of the BIST operation. The method further includes receiving, from each hash engine, a response with information indicating a number of correct results computed by that hash engine. The method further includes comparing the indicated number of correct results to an expected number of correct results for the BIST operation.
1 . A method comprising:
receiving information about one or more parameters for a built-in self-test (BIST) operation;
generating a nonce for each iteration of the BIST operation according to the one or more parameters;
computing a hash value for each iteration of the BIST operation using the nonce as an input to a cryptographic hash function;
transmitting, to a plurality of hash engines, information about the nonce and the hash value for each iteration of the BIST operation;
receiving, from each hash engine of the plurality of hash engines, a response with information indicating a number of correct results computed by the hash engine; and
comparing the indicated number of correct results to an expected number of correct results for the BIST operation.
2 . The method of claim 1 , wherein the cryptographic hash function is selected from the group consisting of a 256-bit secure hashing algorithm (SHA-256), SHA-1, MD5, SHA-3, SHA-512, BLAKE2, or BLAKE3.
3 . The method of claim 1 , wherein the nonce is selected from the group consisting of a 16-bit integer, a 32-bit integer, or a 64-bit integer.
4 . The method of claim 1 , wherein the BIST operation comprises a plurality of iterations, and wherein the one or more parameters indicate a number of iterations for the BIST operation.
5 . The method of claim 1 , wherein the nonce is generated by a state machine of an application-specific integrated circuit (ASIC) comprising the plurality of hash engines.
6 . The method of claim 5 , further comprising determining the expected number of correct results for the BIST operation based at least in part on a number of hash engines on the ASIC and a number of iterations associated with the BIST operation.
7 . The method of claim 5 , further comprising summing the number of correct results computed by each hash engine to determine a cumulative number of correct results computed by the plurality of hash engines.
8 . The method of claim 7 , further comprising determining a hit rate of the ASIC based at least in part on the cumulative number of correct results computed by the plurality of hash engines.
9 . The method of claim 8 , further comprising adjusting at least one member selected from the group consisting of an operating voltage, a clock frequency, or a clock cycle of the ASIC based at least in part on the determined hit rate.
10 . The method of claim 1 , wherein the information about the nonce and the hash value is transmitted in parallel to each of the plurality of hash engines.
11 . A method comprising:
receiving, from a controller, information about a nonce and a hash value for each iteration of a BIST operation;
inserting the nonce into a data pipeline of a hash engine;
receiving an output value from the data pipeline into which the nonce was inserted;
comparing the output value to the hash value provided by the controller;
determining a number of correct results computed by the hash engine during the BIST operation based at least in part on comparing the output value to the hash value provided by the controller; and
transmitting, to the controller, a response with information indicating the number of correct results computed by the hash engine during the BIST operation.
12 . The method of claim 11 , wherein the data pipeline is configured to execute a cryptographic hash function using the nonce as an input.
13 . The method of claim 12 , wherein the cryptographic hash function is selected from the group consisting of SHA-256, SHA-1, MD5, SHA-3, SHA-512, BLAKE2, or BLAKE3.
14 . The method of claim 11 , wherein the nonce is selected from the group consisting of a 16-bit integer, a 32-bit integer, or a 64-bit integer.
15 . The method of claim 11 , wherein the BIST operation comprises a plurality of iterations.
16 . The method of claim 15 , wherein the nonce is generated by a state machine of an ASIC comprising the hash engine.
17 . The method of claim 16 , wherein the ASIC comprises 238 hash engines.
18 . An electronic circuit comprising:
a plurality of hash engines; and
a controller coupled to the plurality of hash engines and configured to perform operations comprising:
receiving an indication of one or more parameters for a BIST operation;
generating a nonce for each iteration of the BIST operation according to the one or more parameters;
computing a hash value for each iteration of the BIST operation using the nonce as an input to a cryptographic hash function;
transmitting, to a plurality of hash engines, information about the nonce and the hash value for each iteration of the BIST operation;
receiving, from each hash engine of the plurality of hash engines, a response with information indicating a number of correct results computed by the hash engine; and
comparing the indicated number of correct results to an expected number of correct results for the BIST operation.
19 . The electronic circuit of claim 18 , wherein the cryptographic hash function is selected from the group consisting of SHA-256, SHA-1, MD5, SHA-3, SHA-512, BLAKE2, or BLAKE3.
20 . The electronic circuit of claim 18 , wherein the nonce is selected from the group consisting of a 16-bit integer, a 32-bit integer, or a 64-bit integer.
21 . The electronic circuit of claim 18 , wherein the BIST operation comprises a plurality of iterations, and wherein the one or more parameters indicate a number of iterations for the BIST operation.
22 . The electronic circuit of claim 18 , wherein the nonce is generated by a state machine of an ASIC comprising the plurality of hash engines.
23 . The electronic circuit of claim 22 , wherein the operations further comprise determining the expected number of correct results for the BIST operation based at least in part on a number of hash engines on the ASIC and a number of iterations associated with the BIST operation.
24 . The electronic circuit of claim 18 , wherein the operations further comprise summing the number of correct results computed by each hash engine to determine a cumulative number of correct results computed by the plurality of hash engines.
25 . The electronic circuit of claim 24 , further comprising determining a respective health status of each hash engine based at least in part on the indicated number of correct results computed by the hash engine.
26 . The electronic circuit of claim 18 , wherein the information about the nonce and the hash value is transmitted in parallel to each of the plurality of hash engines.
27 . An electronic circuit configured to perform operations comprising:
receiving, from a controller, information about a nonce and a hash value for each iteration of a BIST operation;
inserting the nonce into a data pipeline of a hash engine, wherein the data pipeline is configured to execute a cryptographic hash function using the nonce as an input;
receiving an output value from the data pipeline into which the nonce was inserted;
comparing the output value to the hash value provided by the controller;
determining a number of correct results computed by the hash engine during the BIST operation based at least in part on comparing the output value to the hash value provided to the controller; and
transmitting, to the controller, a response with information indicating the number of correct results computed by the hash engine during the BIST operation.
28 . The electronic circuit of claim 27 , wherein the cryptographic hash function is selected from the group consisting of SHA-256, SHA-1, MD5, SHA-3, SHA-512, BLAKE2, or BLAKE3, and
wherein the nonce is selected from the group consisting of a 16-bit integer, a 32-bit integer, or a 64-bit integer.
29 . The electronic circuit of claim 27 , wherein the nonce is generated by a state machine of an ASIC comprising the hash engine.