In-situ scan testing of an integrated circuit device

1 . A system to perform in-situ scan testing in a field operating environment, the system comprising:

an accelerator device comprising a plurality of computing cores, a management controller, and a local memory coupled via an interconnect;

a high bandwidth memory (HBM) device coupled to the accelerator device; and

a host device coupled to the accelerator device via a host interface,

wherein the host device is operable to:

preload test content as a user workload onto the HBM device, wherein the test content includes a test configuration file, and multiple vector sets that each includes a test stimuli vector, an expected result vector, and a mask vector;

load a utility test program onto the local memory of the accelerator device; and

assert a program execution signal to the management controller to initiate the in-situ scan testing of the accelerator device,

wherein, upon receiving the program execution signal, the management controller is operable to execute the utility test program to:

isolate a computing core under test by masking outputs from the computing core under test to the interconnect;

configure a scan testing interface of the accelerator device to select an internal test path that accesses the local memory for scan testing;

apply the test content to perform the in-situ scan testing of the computing core under test; and

write to a predefined address to indicate completion of the in-situ scan testing to the host device, and

wherein the in-situ scan testing of the computing core under test is performed without affecting functional connectivity of the accelerator device with the host device via the host interface.

2 . The system of claim 1 , wherein applying the test content to perform the in-situ scan testing of the computing core under test includes:

configuring the computing core under test into a scan test mode according to the test configuration file; and

for each vector set from the multiple vector sets:

loading the test stimuli vector, the expected result vector, and the mask vector from the HBM device onto the local memory;

providing the test stimuli vector from the local memory to the scan testing interface to apply the test stimuli vector to the computing core under test;

obtaining a response vector from the scan testing interface;

applying the mask vector to the response vector to generate a test result vector;

comparing the test result vector with the expected result vector to determine whether a fault is detected in the computing core under test; and

writing the test result vector to the HBM device.

3 . The system of claim 1 , wherein the host device is further operable to poll the predefined address to determine the completion of the scan testing.

4 . The system of claim 1 , wherein the scan testing interface of the accelerator device is operable to select an external test path that accesses external pins of the accelerator device to perform the scan testing of the accelerator device prior to deployment of the accelerator device into the field operating environment.

5 . A method for performing in-situ scan testing of an integrated circuit (IC) device that is coupled to a main memory, the IC device having a plurality of functional circuit blocks, a management controller, and a local memory coupled via an interconnect, the method comprising:

preloading test content from a host device onto the main memory coupled to the IC device;

loading a utility test program onto the local memory of the IC device;

causing the management controller to execute the utility test program to load the test content from the main memory onto the local memory; and

applying the test content to perform scan testing of one or more of the functional circuit blocks while maintaining functional connectivity with the host device.

6 . The method of claim 5 , wherein causing the management controller to execute the utility test program includes asserting a program execution signal to the management controller to initiate the in-situ scan testing of the IC device.

7 . The method of claim 5 , wherein execution of the utility test program includes isolating the one or more of the functional circuit blocks under test by masking outputs from the one or more of the functional circuit blocks under test to the interconnect.

8 . The method of claim 7 , wherein the IC device includes a block mask register that includes a respective mask configuration bit for each functional circuit block, and wherein outputs of each functional circuit block are gated by the respective mask configuration bit.

9 . The method of claim 5 , wherein the IC device includes a scan testing interface coupled to an internal test path that accesses the local memory and an external test path that accesses external pins of the IC device, and wherein execution of the utility test program includes configuring the scan testing interface to select the internal test path.

10 . The method of claim 5 , wherein the test content is preloaded as a user workload from the host device, and the test content includes a test configuration file, a test stimulus vector, an expected result vector, and a mask vector.

11 . The method of claim 10 , wherein applying the test content includes configuring the one or more of the functional circuit blocks into a scan test mode according to the test configuration file.

12 . The method of claim 10 , wherein applying the test content includes:

providing the test stimulus vector from the local memory to a scan testing interface;

obtaining a response vector from the scan testing interface;

applying the mask vector to the response vector to generate a test result vector; and

comparing the test result vector with the expected result vector to determine whether a fault is detected.

13 . The method of claim 12 , further comprising writing the test result vector to the main memory.

14 . The method of claim 5 , wherein the test content is preloaded as a user workload from the host device, and the test content includes multiple vector sets that each includes a test stimuli vector, an expected result vector, and a mask vector, and wherein the multiple vector sets are loaded into the local memory in a piecemeal manner.

15 . The method of claim 5 , wherein the utility test program provides an address that the management controller writes to for indicating test completion, and wherein the host device polls the address to determine when the in-situ scan testing is complete.

16 . An integrated circuit (IC) device comprising:

a plurality of functional circuit blocks;

an interconnect;

a scan testing interface coupled to the interconnect;

a local memory;

a block mask register configured to store respective mask configuration bits for a corresponding plurality of functional circuit blocks; and

a management controller coupled to the local memory, wherein the management controller is operable to execute a utility test program to perform in-situ scan testing of a functional circuit block by:

isolating the functional circuit block;

configuring the scan testing interface to select an internal test path that accesses the local memory;

loading test content from a main memory into the local memory via the interconnect, wherein the test content is preloaded into the main memory by a host device;

configuring the functional circuit block into a scan test mode; and

applying the test content from the local memory to perform the in-situ scan testing of the functional circuit block while maintaining functional connectivity with the host device.

17 . The IC device of claim 16 , wherein applying the test content includes:

providing a test stimulus vector from the test content to the scan testing interface;

obtaining a response vector from the scan testing interface; and

applying a mask vector from the test content to the response vector to generate a test result vector.

18 . The IC device of claim 17 , wherein applying the test content includes:

comparing the test result vector with an expected result vector from the test content;

writing the test result vector to the main memory upon detection of a fault; and

writing to a predetermined address indicating test completion, wherein the host device polls the predetermined address to determine when the in-situ scan testing is complete.

19 . The IC device of claim 16 , wherein the test content is preloaded as a user workload from the host device, and the test content includes a test configuration file, and wherein the functional circuit block is configured into the scan test mode according to the test configuration file.

20 . The IC device of claim 16 , further comprising a block mask register configured to store respective mask configuration bits for the plurality of functional circuit blocks, wherein isolating the functional circuit block under test includes masking outputs from the functional circuit block to the interconnect by setting a corresponding mask configuration bit in the block mask register for the functional circuit block.