Apparatus and test element group
According to one or more embodiments of the disclosure, an apparatus comprising a plurality of active regions on a semiconductor substrate, an active bridge region connecting two active regions among the plurality of active regions, and a plurality of test circuit elements on the active bridge region and the two active regions.
1 . An apparatus, comprising:
a plurality of active regions on a semiconductor substrate;
an enlarged active region including an active bridge region and at least two adjacent active regions connected by the active bridge region among the plurality of active regions, wherein the enlarged active region is greater in size, at least in a plan view, than other active regions adjacent to the enlarged active region among the plurality of active regions; and
a plurality of test circuit elements on the enlarged active region.
2 . The apparatus according to claim 1 , wherein the enlarged active region has an elongated shape at least in one direction in the plan view.
3 . The apparatus according to claim 2 , wherein
the two active regions are arranged in line along the one direction with a gap therebetween, and
the active bridge region fills the gap.
4 . The apparatus according to claim 2 , wherein the enlarged active region is spaced from the other active regions among the plurality of active regions by at least one opening.
5 . The apparatus according to claim 1 , wherein the test circuit elements include two capacitance contacts on the enlarged active region.
6 . The apparatus according to claim 5 , wherein the test circuit elements further include at least one bit contact on the enlarged active region.
7 . The apparatus according to claim 1 , wherein the test circuit elements include two bit contacts on the enlarged active region.
8 . The apparatus according to claim 7 , wherein the test circuit elements further include at least one capacitance contact on the enlarged active region.
9 . The apparatus according to claim 1 , wherein the test circuit elements include test transistor elements.
10 . An apparatus, comprising:
a plurality of active regions arranged in matrix in a scribe region on a semiconductor substrate;
an active bridge region physically connecting at least first and second active regions arranged adjacently among the plurality of active regions, the active bridge region and the at least first and second active regions forming an enlarged active region at least in a first horizontal direction in a plan view, wherein the enlarged active region has a first horizontal-direction size greater than a third active region adjacent to the enlarged active region among the plurality of active regions; and
a plurality of test circuit elements on the enlarged active region, the plurality of test circuit elements including two capacitance contacts or two bit contacts electrically connected to each other by the enlarged active region.
11 . The apparatus according to claim 10 , wherein
the at least first and second active regions are arranged in line along the first horizontal direction with a gap therebetween, and
the active bridge region fills the gap.
12 . The apparatus according to claim 10 , wherein the two capacitance contacts are coupled to a capacitance.
13 . The apparatus according to claim 10 , wherein the two bit contacts are coupled to a bit line.
14 . The apparatus according to claim 10 , wherein the two capacitance contacts or the two bit contacts are part of a test transistor.
15 . The apparatus according to claim 10 , further comprising a plurality of word lines configured to be turned on and off during testing of a circuit electric property.
16 . A test element group in a scribe region on a semiconductor substrate, comprising:
a plurality of active regions in the scribe region, including:
an enlarged active region as a combination of an active bridge region and two adjacent active regions connected by the active bridge region among the plurality of active regions; and
a non-bridged active region adjacent to the active bridge region among the plurality of active regions, wherein the enlarged active region is greater in size than the non-bridged active region at least in a plan view; and
a plurality of test circuit elements on the enlarged active region.
17 . The test element group according to claim 16 , wherein the enlarged active region has an elongated shape at least in a first horizontal direction in the plan view, having a first size greater than the non-bridged active region in the first horizontal direction and a second size same as the non-bridged active region in a second horizontal direction perpendicular to the first horizontal direction.
18 . The test element group according to claim 17 , wherein
the two active regions are arranged in line along the first horizontal direction with a gap therebetween, and
the active bridge region fills the gap.
19 . The test element group according to claim 16 , wherein the test circuit elements are at least part of a test transistor.
20 . The test element group according to claim 16 , wherein the test element group is at least part of a memory device.