CFAR OS detection hardware with comparison circuitry
In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.
1 . A method comprising:
receiving data samples into a register of a plurality of cells, wherein as each incoming data sample is received into a first cell in the register, previously received data samples are shifted downstream by one cell, the receiving and shifting continuing at least until a first incoming data sample is in a cell under test (CUT) of the register and subsequently received data samples are in respective cells of a first window of cells on an upstream side of the CUT, the register further including a second window of cells on a downstream side of the CUT;
computing a noise level of data samples in the register including:
sorting data samples from the register to provide sorted data samples; and
selecting a Kth ranked data sample from among the sorted data samples as the noise level, wherein a value of K varies in accordance with a number of data samples from the first window of cells and the second window of cells used in the sorting; and
comparing the data sample in the CUT to the noise level.
2 . The method of claim 1 , wherein:
the register further includes an upstream guard cell that is between the first window of cells and the CUT, and a downstream guard cell that is between the CUT and the second window of cells; and
any data sample in either the upstream guard cell or the downstream guard cell is not used in the sorting, computing, and comparing operations.
3 . The method of claim 1 , wherein the computing of the noise level of data samples in the register is repeated after receiving a next incoming data sample.
4 . The method of claim 1 , further comprising:
receiving a next incoming sample and shifting each previously received data sample one cell downstream at each clock cycle.
5 . The method of claim 1 , further comprising:
increasing the value of K as data samples shift into cells of the second window of cells in response to receiving subsequent incoming data samples.
6 . The method of claim 1 , further comprising:
decreasing the value of K as the number of data samples in cells of the first window of cells decreases.
7 . The method of claim 1 , wherein the value of K is a maximum when all cells of the first and second windows of cells have a respective data sample.
8 . The method of claim 1 , wherein the number of cells of each of the first window of cells and the second window of cells is L, and the value of K is:
a first value when all L cells of the first window of cells has a respective data sample and zero to (L/4)−1 cells of the second window of cells has a respective data sample;
a second value when all L cells of the first window of cells has a respective data sample and L/4 to (2L/4)−1 cells of the second window of cells has a respective data sample;
a third value when all L cells of the first window of cells has a respective data sample and 2L/4 to (3L/4)−1 cells of the second window of cells has a respective data sample;
a fourth value when all L cells of the first window of cells has a respective data sample and 3L/4 to (4L/4)−1 cells of the second window of cells has a respective data sample; and
a fifth value when all L cells of both the first window of cells and the second window of cells has a respective data sample.
9 . The method of claim 2 , wherein, when each cell of the register includes a respective data sample, the receiving and shifting includes at each clock cycle:
receiving an incoming data sample in the first cell of the register, shifting each data sample in the register one cell downstream, and shifting the data sample in a last cell of the register out of the register.
10 . The method of claim 9 , further comprising:
updating, at each clock cycle, the sorted data samples based on ranks of a newest incoming data sample, the data sample shifted from a last cell of the first window of cells into the upstream guard cell, the data sample shifted from the downstream guard cell into a first cell of the second window of cells, and the data sample shifted out of the register; and
recomputing, at each clock cycle, the noise level of the data samples in the register after each instance of updating.