Source/sink LDO with reduced dead band
A source/sink LDO is provided with a pre-amplifier that pre-amplifies an error voltage equaling a difference between an output voltage and a reference voltage. The resulting pre-amplification reduces the dead band for the source/sink LDO by the gain of the pre-amplifier.
1 . A source/sink LDO, comprising:
an output node for an output voltage;
a first transistor coupled between the output node and a power supply node for a power supply voltage;
a second transistor coupled between the output node and ground;
a pre-amplifier configured to amplify an error signal to form a pre-amplified error signal, wherein the error signal equals a difference between the output voltage and a reference voltage; and
an error amplifier configured to drive a gate of the first transistor and to drive a gate of the second transistor responsive to the pre-amplified error signal and an offset voltage.
2 . The source/sink LDO of claim 1 , wherein the first transistor and the second transistor each comprises a NMOS transistor.
3 . The source/sink LDO of claim 1 , wherein the pre-amplifier is a fully differential pre-amplifier, and wherein the pre-amplified error signal is a differential pre-amplified error signal having a positive component and a negative component.
4 . The source/sink LDO of claim 3 , wherein the pre-amplifier comprises:
a first current source; and
a differential pair of transistors configured to steer a current from the first current source responsive to the difference between the output voltage and the reference voltage.
5 . The source/sink LDO of claim 4 , wherein the differential pair of transistor comprises:
a first bipolar junction transistor having an emitter coupled to the first current source and a collector coupled to the power supply node through a first resistor; and
a second bipolar junction transistor having an emitter coupled to the first current source and a collector coupled to the power supply node through a second resistor.
6 . The source/sink LDO of claim 5 , wherein the pre-amplifier further comprises:
a third bipolar junction transistor having a collector coupled to ground, an emitter coupled to a base of the first bipolar junction transistor, and a base coupled to an output node for the output voltage;
a second current source coupled between the collector of the third bipolar junction transistor and the power supply node;
a fourth bipolar junction transistor having a collector coupled to ground, an emitter coupled to a base of the second bipolar junction transistor, and a base coupled to a node for the reference voltage; and
a third current source coupled between the collector of the fourth bipolar junction transistor and the power supply node.
7 . The source/sink LDO of claim 5 , wherein the error amplifier comprises:
a first cascode transistor having a first terminal coupled to the collector of the first bipolar junction transistor;
a first diode-connected transistor coupled between a second terminal of the first cascode transistor and ground;
a first current-mirror transistor configured to mirror a current conducted by the first diode-connected transistor;
a second cascode transistor having a first terminal coupled to the collector of the second bipolar junction transistor;
a second diode-connected transistor coupled between a second terminal of the first cascode transistor and ground;
a second current-mirror transistor configured to mirror a current conducted by the second diode-connected transistor and having a terminal coupled to the gate of the first transistor; and
a first current mirror configured to mirror a current conducted by the second current-mirror transistor to the gate of the first transistor.
8 . The source/sink LDO of claim 7 , wherein the first cascode transistor and the second cascode transistor each comprises a PMOS transistor, the first diode-connected transistor and the second diode-connected transistor each comprises a diode-connected NMOS transistor, and the first current-mirror transistor and the second current-mirror transistor each comprises a current-mirror NMOS transistor.
9 . The source/sink LDO of claim 8 , wherein the error amplifier further comprises an extra NMOS transistor having a gate coupled to a gate of the second diode-connected transistor, a source coupled to ground; and a drain coupled to the gate of the first transistor.
10 . The source/sink LDO of claim 8 , further comprising:
a first cross-coupled NMOS transistor having a source coupled to ground, a gate coupled to a gate of the first diode-connected transistor, and a drain coupled to a drain of the second cascode transistor; and
a second cross-coupled NMOS transistor having a source coupled to ground, a gate coupled to a gate of the second diode-connected transistor, and a drain coupled to a drain of the first cascode transistor.
11 . The source/sink LDO of claim 7 , wherein the error amplifier further comprises:
a third transistor having a source coupled to ground, a gate coupled to a gate of the first diode-connected transistor; and a drain coupled to the gate of the second transistor;
a fourth transistor having a source coupled to ground and a gate coupled to a gate of the second diode-connected transistor; and
a second current mirror configured to mirror a current conducted by the fourth transistor to the gate of the second transistor.
12 . The source/sink LDO of claim 11 , wherein the error amplifier further comprises:
an extra NMOS transistor having a source coupled to ground, a gate coupled to the gate of the first diode-connected transistor, and a drain coupled to the gate of the second transistor.
13 . The source/sink LDO of claim 11 , wherein the first current mirror comprises a first pair of PMOS transistors, and the second current mirror comprises a second pair of PMOS transistors.
14 . A method of operation of a source/sink LDO comprising:
pre-amplifying a difference between an output voltage and a reference voltage to provide a differential pre-amplified voltage;
driving a gate of a first transistor coupled between an output node for the output voltage and a power supply node for a power supply voltage responsive to a negative of the differential pre-amplified voltage minus an offset voltage; and
driving a gate of a second transistor coupled between the output node and ground responsive to the differential pre-amplified voltage minus the offset voltage.
15 . The method of claim 14 , wherein pre-amplifying the difference between the output voltage and the reference voltage comprises steering a tail current through a differential pair of bipolar junction transistors responsive to the difference to develop the differential pre-amplified voltage across a pair of collectors for the differential pair of bipolar junction transistors.
16 . A source/sink LDO, comprising:
a pre-amplifier configured to pre-amplify an error voltage into a pre-amplified error voltage having a positive component and a negative component;
an offset voltage circuit configured to subtract an offset voltage from the negative component to form a first voltage and to add the offset voltage to the negative component to form a second voltage;
a first differential amplifier configured to amplify a difference between the first voltage and the positive component; and
a second differential amplifier configured to amplify a difference between the positive component and the second voltage.
17 . The source/sink LDO of claim 16 , further comprising:
a first transistor coupled between a power supply node and an output node for the source/sink LDO, wherein an output terminal of the first differential amplifier is coupled to a gate of the first transistor; and
a second transistor coupled between the output node for the source/sink LDO and ground, wherein an output terminal of the second differential amplifier is coupled to a gate of the second transistor.
18 . The source/sink LDO of claim 17 , wherein the first transistor and the second transistor each comprises an NMOS transistor.
19 . The source/sink LDO of claim 17 , wherein the output node for the source/sink LDO is coupled to a non-inverting input terminal of the pre-amplifier and wherein a node for a reference voltage is coupled to an inverting input terminal of the pre-amplifier.
20 . The source/sink LDO of claim 17 , wherein the source/sink LDO is configured to bias a termination node of a double data rate memory.