Controlling instruction issue rate using credit-based mechanisms in processor devices

1 . A processor device, comprising:

an instruction processing circuit comprising a plurality of pipeline stage circuits including a scheduling stage circuit comprising a reservation station (RS) circuit;

a credit logic circuit communicatively coupled to the RS circuit and comprising a credit counter;

the credit logic circuit configured to:

receive an instruction issue indication for an instruction from the RS circuit during a static time interval;

decrement a value of the credit counter;

determine whether the value of the credit counter equals or is less than a blocking threshold; and

responsive to determining that the value of the credit counter equals or is less than the blocking threshold, assert a block signal to the RS circuit; and

the RS circuit configured to:

receive the block signal; and

responsive to receiving the block signal, block further instruction issuance during the static time interval.

2 . The processor device of claim 1 , wherein the RS circuit is further configured to:

determine whether the block signal is asserted; and

responsive to determining that the block signal is not asserted:

issue the instruction; and

transmit the instruction issue indication to the credit logic circuit.

3 . The processor device of claim 1 , wherein:

the credit logic circuit is further configured to:

deassert the block signal to the RS circuit;

receive a throttle rate from a power management circuit; and

set the value of the credit counter to a replenishment amount corresponding to the throttle rate;

the throttle rate indicates a percentage of processor cycles of the static time interval during which instructions may issue; and

the replenishment amount comprises a product of the percentage and a count of the processor cycles of the static time interval.

4 . The processor device of claim 1 , wherein the blocking threshold comprises a value of zero (0).

5 . The processor device of claim 1 , wherein the blocking threshold comprises a count of processor cycles of communications latency between the credit logic circuit and the RS circuit.

6 . The processor device of claim 3 , wherein the credit logic circuit is further configured to, at a start of a next static time interval:

deassert the block signal to the RS circuit; and

reset the credit counter to the replenishment amount.

7 . The processor device of claim 3 , wherein the credit logic circuit is further configured to, at a start of a next static time interval:

deassert the block signal to the RS circuit; and

add the replenishment amount to the value of the credit counter.

8 . The processor device of claim 7 , wherein the credit logic circuit is further configured to:

determine whether the value of the credit counter exceeds a maximum threshold; and

responsive to determining that the value of the credit counter exceeds the maximum threshold, set the value of the credit counter to the maximum threshold.

9 . The processor device of claim 1 , integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

10 . A processor device, comprising:

means for receiving an instruction issue indication for an instruction from a reservation station (RS) circuit during a static time interval;

means for decrementing a value of a credit counter;

means for determining whether the value of the credit counter equals or is less than a blocking threshold;

means for asserting a block signal to the RS circuit, responsive to determining that the value of the credit counter equals or is less than the blocking threshold;

means for receiving the block signal; and

means for blocking further instruction issuance during the static time interval, responsive to receiving the block signal.

11 . A method for controlling instruction issue rate using credit-based mechanisms in processor devices, comprising:

receiving, by a credit logic circuit of a processor device, an instruction issue indication for an instruction from a reservation station (RS) circuit of the processor device during a static time interval;

decrementing, by the credit logic circuit, a value of a credit counter;

determining, by the credit logic circuit, that the value of the credit counter equals or is less than a blocking threshold;

responsive to determining that the value of the credit counter equals or is less than the blocking threshold, asserting, by the credit logic circuit, a block signal to the RS circuit;

receiving, by the RS circuit, the block signal; and

responsive to receiving the block signal, blocking, by the RS circuit, further instruction issuance during the static time interval.

12 . The method of claim 11 , further comprising:

determining, by the RS circuit, that the block signal is not asserted; and

responsive to determining that the block signal is not asserted:

issuing the instruction; and

transmitting the instruction issue indication to the credit logic circuit.

13 . The method of claim 11 , further comprising:

deasserting, by the credit logic circuit, the block signal to the RS circuit;

receiving, by the credit logic circuit, a throttle rate from a power management circuit; and

setting, by the credit logic circuit, the value of the credit counter of the credit logic circuit to a replenishment amount corresponding to the throttle rate;

wherein:

the throttle rate indicates a percentage of processor cycles of the static time interval during which instructions may issue; and

the replenishment amount comprises a product of the percentage and a count of the processor cycles of the static time interval.

14 . The method of claim 11 , wherein the blocking threshold comprises a value of zero (0).

15 . The method of claim 11 , wherein the blocking threshold comprises a count of processor cycles of communications latency between the credit logic circuit and the RS circuit.

16 . The method of claim 13 , further comprising, at a start of a next static time interval:

deasserting, by the credit logic circuit, the block signal to the RS circuit; and

resetting, by the credit logic circuit, the credit counter to the replenishment amount.

17 . The method of claim 13 , further comprising, at a start of a next static time interval:

deasserting, by the credit logic circuit, the block signal to the RS circuit; and

adding, by the credit logic circuit, the replenishment amount to the value of the credit counter.

18 . The method of claim 17 , further comprising:

determining, by the credit logic circuit, that the value of the credit counter exceeds a maximum threshold; and

responsive to determining that the value of the credit counter exceeds the maximum threshold, setting, by the credit logic circuit, the value of the credit counter to the maximum threshold.

19 . A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device, cause the processor device to:

receive an instruction issue indication for an instruction from a reservation station (RS) circuit during a static time interval;

decrement a value of a credit counter;

determine whether the value of the credit counter equals or is less than a blocking threshold;

responsive to determining that the value of the credit counter equals or is less than the blocking threshold, assert a block signal to the RS circuit;

receive the block signal; and

responsive to receiving the block signal, block further instruction issuance during the static time interval.

20 . The non-transitory computer-readable medium of claim 19 , wherein the computer-executable instructions further cause the processor device to:

determine whether the block signal is asserted; and

responsive to determining that the block signal is not asserted:

issue the instruction; and

transmit the instruction issue indication.