Memory storing metadata and memory system

1 . A memory comprising:

a data transmission/reception circuit; and

a memory bank including a plurality of cell arrays, wherein:

when a metadata mode is activated, data and metadata received through the data transmission/reception circuit are distributed to and stored in the plurality of cell arrays, and

when the metadata mode is deactivated, the data received through the data transmission/reception circuit are distributed to and stored in cell arrays except one or more no-access cell arrays, among the plurality of cell arrays,

wherein a first number (N) of cases of a column address that is accessible when the metadata mode is activated and a second number (M) of cases of the column address that is accessible when the metadata mode is deactivated are different from each other, where N is an integer equal to or greater than 2, and M is greater than N, and

wherein:

a range of a value of the column address, when the metadata mode is deactivated, comprises a first range and a second range,

when the value of the column address is within the first range, columns having an identical location in each of the cell arrays except the one or more no-access cell arrays, among the plurality of cell arrays, are accessed, and

when the value of the column address is within the second range, columns having different locations in each of the cell arrays except the one or more no-access cell arrays, among the plurality of cell arrays, are accessed.

2 . The memory of claim 1 , wherein the one or more no-access cell arrays are determined by an address.

3 . The memory of claim 2 , wherein the address is a column address.

4 . The memory of claim 1 , wherein the second number of cases of the column address is greater than the first number of cases of the column address.

5 . The memory of claim 1 , wherein when the metadata mode is activated, columns having an identical location in the plurality of cell arrays are accessed.

6 . The memory of claim 1 , further comprising a data bus for transferring data between the data transmission/reception circuit and the memory bank,

wherein the memory bank further comprises a data selection circuit for a connection between the data bus and cell arrays to be accessed, among the plurality of cell arrays.

7 . The memory of claim 1 , wherein the data transmission/reception circuit is configured to:

receive the metadata through a plurality of data pads after receiving the data through the plurality of data pads when the metadata mode is activated; and

receive the data through the plurality of data pads when the metadata mode is deactivated.

8 . The memory of claim 1 , wherein the memory comprises a plurality of memory banks.

9 . A memory comprising:

a data transmission/reception circuit;

an ECC engine; and

a memory bank including plurality of cell arrays, wherein:

the ECC engine is configured to generate an error correction code by using data and metadata received through the data transmission/reception circuit when a metadata mode is activated, and generate the error correction code by using the data received through the data transmission/reception circuit when the metadata mode is deactivated,

when the metadata mode is activated, the data, the metadata, and the error correction code are distributed to and stored in the plurality of cell arrays, and

when the metadata mode is deactivated, the data and the error correction code are distributed to and stored in cell arrays except one or more no-access cell arrays, among the plurality of cell arrays,

wherein a first number (N) of cases of a column address that is accessible when the metadata mode is activated and a second number (M) of cases of the column address that is accessible when the metadata mode is deactivated are different from each other, where N is an integer equal to or greater than 2, and M is greater than N, and

wherein:

a range of a value of the column address, when the metadata mode is deactivated, comprises a first range and a second range,

when the value of the column address is within the first range, columns having an identical location in each of the cell arrays except the one or more no-access cell arrays, among the plurality of cell arrays, are accessed, and

when the value of the column address is within the second range, columns having different locations in each of the cell arrays except the one or more no-access cell arrays, among the plurality of cell arrays, are accessed.

10 . The memory of claim 9 , wherein the one or more no-access cell arrays are determined by an address.

11 . The memory of claim 10 , wherein the address is a column address.

12 . The memory of claim 9 , wherein the second number of cases of the column address is greater than the first number of cases of the column address.

13 . The memory of claim 9 , wherein when the metadata mode is activated, columns having an identical location in the plurality of cell arrays are accessed.

14 . The memory of claim 9 , wherein the memory bank further comprises a data selection circuit configured to:

transmit the data, the metadata, and the error correction code to cell arrays to be accessed, among the plurality of cell arrays when the metadata mode is activated; and

transmit the data and the error correction code to the cell arrays to be accessed, among the plurality of cell arrays, when the metadata mode is deactivated.

15 . The memory of claim 9 , wherein the data transmission/reception circuit is configured to:

receive the metadata through a plurality of data pads after receiving the data through the plurality of data pads when the metadata mode is activated; and

receive the data through the plurality of data pads when the metadata mode is deactivated.

16 . The memory of claim 9 , wherein the memory comprises a plurality of memory banks.

17 . A memory system comprising:

a memory in which a number of cases of a column address that is accessible is changed depending on a set mode; and

a memory controller configured to control the memory, the memory controller including an address conversion circuit configured to convert a system address into a memory address for accessing the memory,

wherein the system address is converted into the memory address according to a method that is changed depending on the set mode,

wherein:

the memory address comprises a bank address, a row address, and a column address, and

the number of cases of the column address that is accessible when a metadata mode is activated is N, where N is an integer equal to or greater than 2, and

the number of cases of the column address that is accessible when the metadata mode is deactivated is M, where M is an integer greater than N, and

wherein the address conversion circuit is configured to:

convert a quotient that is obtained by dividing a value of the system address by N into the bank address and the row address, and converts a remainder into the column address when the metadata mode is activated, and

convert a quotient that is obtained by dividing the value of the system address by M into the bank address and the row address, and converts a remainder into the column address when the metadata mode is deactivated.

18 . The memory system of claim 17 , wherein the memory comprises:

a data transmission/reception circuit; and

a memory bank including plurality of cell arrays, wherein:

when a metadata mode is activated, data and metadata received through the data transmission/reception circuit are distributed to and stored in the plurality of cell arrays, and

when the metadata mode is deactivated, the data received through the data transmission/reception circuit are distributed to and stored in cell arrays except one or more no-access cell arrays, among the plurality of cell arrays.