Protecting data stored in memory

1 . A method performed by a memory device comprising memory, the memory device coupled to a host device, the method comprising:

receiving, at the memory device, a command from the host device to read a portion of the memory;

determining, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads; and

providing, by the memory device, based on the command, the host device with data stored in the portion of the memory using a plurality of throttled read operations, wherein each throttled read operation of the plurality of throttled read operations:

comprises no more than the threshold number of reads, and

is performed based on the delay;

wherein providing the data using the plurality of throttled read operations comprises: reading a first portion of the data using the threshold number of reads;

after reading the first portion of the data, waiting for an amount of time greater than or equal to the delay; and

after waiting for the amount of time greater than or equal to the delay, reading a second portion of the data using the threshold number of reads.

2 . The method of claim 1 , wherein the portion of the memory comprises a zoned namespace, the method further comprising:

determining relatively vulnerable logical block addresses (LBAs) and relatively invulnerable LBAs of the zoned namespace; and

after providing the data of the relatively vulnerable LBAs, providing data of the relatively invulnerable LBAs using a plurality of unthrottled read operations, wherein:

the plurality of throttled read operations provide the data from only the relatively vulnerable LBAs.

3 . The method of claim 1 , further comprising determining a relative vulnerability of the portion of the memory, wherein:

determining the relative vulnerability is based on at least one of a voltage threshold or an error check; and

determining the threshold number of reads and the delay is based on the relative vulnerability of the portion of the memory.

4 . The method of claim 1 , further comprising tracking how many throttled read operations of the plurality of throttled read operations are performed.

5 . The method of claim 1 , wherein at least one of the threshold number of reads or the delay associated with the threshold number of reads is based on a relative vulnerability of the portion of the memory to corruption.

6 . The method of claim 1 , wherein the threshold number of reads comprises a plurality of thresholds and the delay comprises a plurality of delays, wherein each respective threshold and each respective delay is associated with a particular subportion of the portion of the memory based on a relative vulnerability of the particular subportion.

7 . The method of claim 1 , further comprising, after providing the host device with the data stored in the portion of the memory, writing the data to another portion of the memory.

8 . A method performed by a memory device comprising memory, the memory device coupled to a host device, the method comprising:

receiving, at the memory device, a command from the host device to read a portion of the memory;

determining, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads;

providing, by the memory device, based on the command, the host device with data stored in the portion of the memory using a plurality of throttled read operations, wherein each throttled read operation of the plurality of throttled read operations:

comprises no more than the threshold number of reads, and

is performed based on the delay:

tracking, for each throttled read operation, a last logical block address (LBA) for which data was provided; and

causing each subsequent throttled read operation to initially provide the host device with data stored in an LBA that is subsequent to the last LBA.

9 . A method performed by a memory device comprising memory, the memory device coupled to a host device, the method comprising:

receiving, at the memory device, a command from the host device to read a portion of the memory;

determining, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads;

providing, by the memory device, based on the command, the host device with data stored in the portion of the memory using a plurality of throttled read operations, wherein each throttled read operation of the plurality of throttled read operations:

comprises no more than the threshold number of reads, and

is performed based on the delay; and

after completing each throttled read operation, providing a message to the host device, wherein the message comprises:

a command interrupted status code, and

a time associated with a subsequent throttled read operation, wherein the time corresponds to the delay.

10 . A system comprising a host device communicatively coupled to a memory device, the memory device comprising memory and processing circuitry to:

receive, at the memory device, a command from the host device to read a portion of the memory;

determine, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads; and

provide, by the memory device, based on the command, the host device with data stored in the portion of the memory using a plurality of throttled read operations, wherein each throttled read operation of the plurality of throttled read operations:

comprises no more than the threshold number of reads, and

is performed based on the delay;

wherein the processing circuitry is to provide the data using the plurality of throttled read operations by:

reading a first portion of the data using the threshold number of reads;

after reading the first portion of the data, waiting for an amount of time greater than or equal to the delay; and

after waiting for the amount of time greater than or equal to the delay, reading a second portion of the data using the threshold number of reads.

11 . The system of claim 10 , wherein the portion of the memory comprises a zoned namespace, and wherein the processing circuitry is further to:

determine, based on a voltage threshold, relatively vulnerable logical block addresses (LBAs) and relatively invulnerable LBAs of the zoned namespace; and

after providing the data of the relatively vulnerable LBAs, providing data of the relatively invulnerable LBAs using a plurality of unthrottled read operations, wherein:

the plurality of throttled read operations provide the data from only the relatively vulnerable LBAs.

12 . The system of claim 10 , wherein the processing circuitry is further to determine a relative vulnerability of the portion of the memory, wherein:

to determine the relative vulnerability is based on at least one of a voltage threshold or an error check; and

to determine the threshold number of reads and the delay is based on the relative vulnerability of the portion of the memory.

13 . The system of claim 10 , wherein the processing circuitry is further to track how many throttled read operations of the plurality of throttled read operations are performed.

14 . The system of claim 10 , wherein at least one of the threshold number of reads or the delay associated with the threshold number of reads is based on a relative vulnerability of the portion of the memory to corruption.

15 . The system of claim 10 , wherein the threshold number of reads comprises a plurality of thresholds and the delay comprises a plurality of delays, wherein each respective threshold and each respective delay is associated with a particular subportion of the portion of the memory based on a relative vulnerability of the particular subportion.

16 . The system of claim 10 , wherein the processing circuitry is further to, after providing the host device with the data stored in the portion of the memory, write the data to another portion of the memory.

17 . A system comprising a host device communicatively coupled to a memory device, the memory device comprising memory and processing circuitry to:

receive, at the memory device, a command from the host device to read a portion of the memory;

determine, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads;

provide, by the memory device, based on the command, the host device with data stored in the portion of the memory using a plurality of throttled read operations, wherein each throttled read operation of the plurality of throttled read operations:

comprises no more than the threshold number of reads, and

is performed based on the delay:

track, for each throttled read operation, a last logical block address (LBA) for which data was provided; and

cause each subsequent throttled read operation to initially provide the host device with data stored in an LBA that is subsequent to the last LBA.

18 . A system comprising a host device communicatively coupled to a memory device, the memory device comprising memory and processing circuitry to:

receive, at the memory device, a command from the host device to read a portion of the memory;

determine, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads;

provide, by the memory device, based on the command, the host device with data stored in the portion of the memory using a plurality of throttled read operations, wherein each throttled read operation of the plurality of throttled read operations:

comprises no more than the threshold number of reads, and

is performed based on the delay; and

after completing each throttled read operation, provide a message to the host device, wherein the message comprises:

a command interrupted status code, and

a time associated with a subsequent throttled read operation, wherein the time corresponds to the delay.