Partitioning system data from user data in memory
The present disclosure includes apparatuses, methods, and systems for partitioning system data from user data in memory. In an example, a method can include receiving system data at a memory, assigning the system data a first address within a first range of memory addresses, storing the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses, receiving user data, assigning the user data a second address within a second range of memory addresses, and storing the user data in a second portion of the memory operated with a second set of trim settings in response to the user having the second address within the second range of addresses.
1 . A method, comprising:
receiving system data at a memory;
assigning the system data a first address within a first range of memory addresses;
storing the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses;
receiving user data;
assigning the user data a second address within a second range of memory addresses; and
storing the user data in a second portion of the memory operated with a second set of trim settings in response to the user data having the second address within the second range of memory addresses, wherein the first set of trim settings or the second set of trim settings comprise at least one of: a programming frequency or a programming time length.
2 . The method of claim 1 , wherein the method includes identifying data as the system data or the user data based on a sender address included with the data.
3 . The method of claim 1 , wherein the method includes pre-defining access rights for the first portion of the memory and the second portion of the memory when partitioning the memory.
4 . The method of claim 1 , wherein the method includes partitioning the first portion of the memory from the second portion of the memory prior to a user operating the memory.
5 . The method of claim 1 , wherein the first range of memory addresses and the second range of memory addresses are fixed across power cycles of the memory.
6 . An apparatus, comprising:
memory; and
trim circuitry configured to:
receive system data at the memory;
assign the system data a first address within a first range of memory addresses in response to receiving the system data;
store the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses;
receive user data;
assign the user data a second address within a second range of memory addresses in response to receiving the user data; and
store the user data in a second portion of the memory operated with a second set of trim settings in response to the user data having the second address within the second range of memory addresses, wherein the first set of trim settings or the second set of trim settings comprise at least one of: a programming frequency or a programming time length.
7 . The apparatus of claim 6 , wherein the trim circuitry is included in a controller.
8 . The apparatus of claim 6 , wherein the trim circuitry is included in a non-volatile memory die.
9 . The apparatus of claim 6 , wherein the trim circuitry comprises an application specific integrated circuit (ASIC).
10 . The apparatus of claim 6 , wherein the first portion of the memory operated with the first set of trim settings is tailored to memory cell endurance.
11 . The apparatus of claim 6 , wherein the second portion of the memory operated with the second set of trim settings is tailored to data retention.
12 . The apparatus of claim 6 , wherein the first set of trim settings or the second set of trim settings are used to adjust a desired threshold voltage distribution.
13 . The apparatus of claim 6 , wherein the trim circuitry is configured to issue a set trim command.
14 . The apparatus of claim 13 , wherein the first portion of the memory is operated with the first set of trim settings in response to the set trim command.
15 . The apparatus of claim 13 , wherein the second portion of the memory is operated with the second set of trim settings in response to the set trim command.
16 . A system, comprising:
a host; and
a memory device coupled to the host, wherein the memory device comprises:
a memory; and
a controller coupled to the memory, the controller including circuitry configured to:
receive system data at the memory from the host;
assign the system data a first address within a first range of memory addresses;
store the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses;
receive user data at the memory from the host;
assign the user data a second address within a second range of memory addresses; and
store the user data in a second portion of the memory operated with a second set of trim settings in response to the user data having the second address within the second range of memory addresses, wherein the first set of trim settings or the second set of trim settings comprise at least one of: a programming frequency or a programming time length.
17 . The system of claim 16 , wherein the first set of trim settings and the second set of trim settings include operating parameters.
18 . The system of claim 17 , wherein the operating parameters are associated with operations including at least one of: program, program verify, erase, erase verify, or sense.
19 . The system of claim 16 , wherein the controller is configured to identify data as the system data or the user data based on metadata.