Inverse erase for memory components
The disclosed system configures a system component, such as a memory sub-system controller, to efficiently erase memory blocks. The controller receives a request to erase an individual memory component of a set of memory components. The controller applies an erase pulse to the individual memory component in response to the request. The controller, following application of the erase pulse, applies a pre-program pulse to the individual memory component.
1 . A system comprising:
a set of memory components of a memory sub-system; and
a processing device operatively coupled to the set of memory components, the processing device being programmed to perform operations comprising:
receiving a request to erase an individual memory component of the set of memory components;
applying an erase pulse to the individual memory component in response to the request; and
following application of the erase pulse, applying a pre-program pulse to the individual memory component, the pre-program pulse raising one or more voltage levels of cells of the individual memory component that are below a threshold voltage level by a specified amount.
2 . The system of claim 1 , wherein the erase pulse comprises an outgoing pattern.
3 . The system of claim 2 , wherein the outgoing pattern is a solid pattern comprising one or more voltage levels that are within a threshold range of a neutral threshold voltage of the individual memory component.
4 . The system of claim 1 , the operations comprising:
determining that the individual memory component comprises a good bad block (GBB), the GBB being a block that has been transitioned into bad block status after initially being in good block status during manufacture of the memory sub-system.
5 . The system of claim 4 , wherein the erase pulse comprises a first erase pulse, the operations comprising:
generating a second erase pulse following the first erase pulse and prior to the pre-program pulse in response to determining that the individual memory component comprises the GBB.
6 . The system of claim 5 , wherein the second erase pulse is at a different trim level than the first erase pulse.
7 . The system of claim 5 , the operations comprising:
adding a threshold voltage corresponding to the GBB to the first erase pulse to generate the second erase pulse.
8 . The system of claim 1 , wherein the request comprises a sanitize operation to erase all of the set of memory components of the memory sub-system including all user blocks.
9 . The system of claim 1 , the operations comprising:
preventing performing a verify operation between application of the erase pulse and application of the pre-program pulse.
10 . A method comprising:
receiving a request to erase an individual memory component of a set of memory components;
applying an erase pulse to the individual memory component in response to the request; and
following application of the erase pulse, applying a pre-program pulse to the individual memory component, the pre-program pulse being shorter than the erase pulse.
11 . The method of claim 10 , wherein the erase pulse comprises an outgoing pattern.
12 . The method of claim 11 , wherein the outgoing pattern is a solid pattern comprising one or more voltage levels that are within a threshold range of a neutral threshold voltage of the individual memory component.
13 . The method of claim 10 , comprising:
determining that the individual memory component comprises a good bad block (GBB), the GBB being a block that has been transitioned into bad block status after initially being in good block status during manufacture of a memory sub-system comprising the set of memory components.
14 . The method of claim 13 , wherein the erase pulse comprises a first erase pulse, comprising:
generating a second erase pulse following the first erase pulse and prior to the pre-program pulse in response to determining that the individual memory component comprises the GBB.
15 . The method of claim 14 , wherein the second erase pulse is at a different trim level than the first erase pulse.
16 . The method of claim 14 , comprising:
adding a threshold voltage corresponding to the GBB to the first erase pulse to generate the second erase pulse.
17 . The method of claim 10 , wherein the pre-program pulse is shorter than the erase pulse.
18 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving a request to erase an individual memory component of a set of memory components;
applying an erase pulse to the individual memory component in response to the request; and
following application of the erase pulse, applying a pre-program pulse to the individual memory component, the pre-program pulse raising one or more voltage levels of cells of the individual memory component that are below a threshold voltage level by a specified amount.
19 . The non-transitory computer-readable storage medium of claim 18 , wherein the erase pulse comprises an outgoing pattern.
20 . The non-transitory computer-readable storage medium of claim 18 , the operations comprising:
preventing performing a verify operation between application of the erase pulse and application of the pre-program pulse.