Two-dimensional data access for volatile memory

1 . An apparatus, comprising:

multiple arrays each comprising a respective plurality of memory cells, wherein a memory bank comprises each of the multiple arrays; and

circuitry comprising:

multiple column decoder circuits each coupled to a different respective array of the multiple arrays, and

multiple row decoder circuits each coupled to a different respective array of the multiple arrays,

the circuitry to perform a memory access operation to access bits each at a different respective array of the multiple arrays, wherein the memory access operation is to be based on each of a row address, a column address, and a control signal which is to indicate an arrangement of the bits relative to each other, wherein the circuitry to perform the memory access operation comprises:

the multiple column decoder circuits each to select a respective column of the respective array based on the column address; and

the multiple row decoder circuits to perform either of:

a selection of each row in a first set of rows based on an indication of a first arrangement of the bits by the control signal; and

a selection of rows each of a different respective set of rows of multiple sets of rows based on an indication of a second arrangement of the bits by the control signal;

wherein:

the first arrangement is different than the second arrangement;

the multiple sets of rows comprise the first set of rows; and

for each set of rows of the multiple sets of rows:

each row of the set of rows is a row of a different respective array of the multiple arrays; and

for each array of the multiple arrays, the set of rows comprises a respective row of the array.

2 . The apparatus of claim 1 , wherein:

the row address is a first row address;

the circuitry further comprises an offset generator circuit which is coupled to receive:

the control signal; and

a first address signal which is to comprise an identifier of the row address; and

for each row decoder circuit of the multiple row decoder circuits, the offset generator circuit is to:

determine a respective address offset value based on the control signal;

determine a respective second row address based on the first row address and the respective address offset value; and

transmit to the row decoder circuit a respective second address signal which is to comprise an identifier of the respective second row address.

3 . The apparatus of claim 1 , wherein:

each of the multiple row decoder circuits is coupled to receive a first address signal which is to comprise an identifier of the row address; and

one or more of the multiple row decoder circuits are each coupled to receive the control signal.

4 . The apparatus of claim 3 , wherein the one or more of the multiple row decoder circuits are each to:

determine a respective address offset amount based on the control signal; and

select a respective row of the respective array based on the first address signal and the respective address offset amount.

5 . The apparatus of claim 1 , wherein an embedded memory comprises the multiple arrays.

6 . A system, comprising:

a processor;

a memory device comprising:

multiple arrays which each comprise a respective plurality of memory cells, wherein a memory bank of the memory device comprises each of the multiple arrays;

multiple column decoder circuits each coupled to a different respective array of the multiple arrays; and

multiple row decoder circuits each coupled to a different respective array of the multiple arrays; and

a controller communicatively coupled to the processor and the memory device, the memory device comprising circuitry to signal the memory device to perform a memory access operation which is to access bits each at a different respective array of the multiple arrays, wherein the memory access operation is to be based on each of a row address, a column address, and a control signal which is to indicate an arrangement of the bits relative to each other, wherein the memory device to perform the memory access operation comprises:

the multiple column decoder circuits each to select a respective column of the respective array based on the column address; and

the multiple row decoder circuits to perform either of:

a selection of each row in a first set of rows based on an indication of a first arrangement of the bits by the control signal; and

a selection of rows each of a different respective set of rows of multiple sets of rows based on an indication of a second arrangement of the bits by the control signal;

wherein:

the first arrangement is different than the second arrangement;

the multiple sets of rows comprise the first set of rows; and

for each set of rows of the multiple sets of rows:

each row of the set of rows is a row of a different respective array of the multiple arrays; and

for each array of the multiple arrays, the set of rows comprises a respective row of the array.

7 . The system of claim 6 , wherein:

the row address is a first row address;

the circuitry further comprises an offset generator circuit which is coupled to receive:

the control signal; and

a first address signal which is to comprise an identifier of the row address; and

for each row decoder circuit of the multiple row decoder circuits, the offset generator circuit is to:

determine a respective address offset value based on the control signal;

determine a respective second row address based on the first row address and the respective address offset value; and

transmit to the row decoder circuit a respective second address signal which is to comprise an identifier of the respective second row address.

8 . The system of claim 7 , wherein

each of the multiple row decoder circuits is coupled to receive a first address signal which is to comprise an identifier of the row address; and

one or more of the multiple row decoder circuits are each coupled to receive the control signal.

9 . The system of claim 8 , wherein the one or more of the multiple row decoder circuits are each to:

determine a respective address offset amount based on the control signal; and

select a respective row of the respective array based on the first address signal and the respective address offset amount.

10 . The system of claim 6 , wherein the controller is further to:

provide a column-wise burst read operation.

11 . The system of claim 10 , wherein the controller is further to:

transpose data from the multiple arrays after the column-wise burst read operation.

12 . The system of claim 6 , wherein the processor, the memory device, and the controller are all integrated on a same integrated circuit die.

13 . The system of claim 6 , wherein the processor, the memory device, and the controller are all integrated on a two or more integrated circuit die of a same multi-die package.

14 . A method, comprising:

receiving a row address and a column address each of a memory access command;

receiving a control signal; and

performing a memory access operation based on each of the row address, the column address, and the control signal;

wherein:

the multiple arrays each comprise a respective plurality of memory cells;

a memory bank comprises each of the multiple arrays;

multiple column decoder circuits are each coupled to a different respective array of the multiple arrays;

multiple row decoder circuits are each coupled to a different respective array of the multiple arrays;

the memory access operation is to access bits each at a different respective array of the multiple arrays;

the control signal which indicates an arrangement of the bits relative to each other;

performing the memory access operation comprises:

the multiple column decoder circuits each selecting a respective column of the respective array based on the column address; and

the multiple row decoder circuits performing either of:

a selection of each row in a first set of rows based on an indication of a first arrangement of the bits by the control signal; and

a selection of rows each of a different respective set of rows of multiple sets of rows based on an indication of a second arrangement of the bits by the control signal;

the first arrangement is different than the second arrangement;

the multiple sets of rows comprise the first set of rows; and

for each set of rows of the multiple sets of rows:

each row of the set of rows is a row of a different respective array of the multiple arrays; and

for each array of the multiple arrays, the set of rows comprises a respective row of the array.

15 . The method of claim 14 , wherein:

the row address is a first row address; and

the method further comprises:

for each row decoder circuit of the multiple row decoder circuits:

determining a respective address offset value based on the control signal;

determining a respective second row address based on the first row address and the respective address offset value; and

transmitting to the row decoder circuit a respective address signal which is to comprise an identifier of the respective second row address.

16 . The method of claim 14 , wherein:

each of the multiple row decoder circuits receives a first address signal which comprises an identifier of the row address; and

one or more of the multiple row decoder circuits each receive the control signal.

17 . The method of claim 16 , wherein the one or more of the multiple row decoder circuits each:

determine a respective address offset amount based on the control signal; and

select a respective row of the respective array based on the first address signal and the respective address offset amount.