Reordering memory controller
A memory controller includes a request queue and associated logic for efficiently managing the request queue based on various timing constraints of the memory device. A single request queue for the memory device stores read and write requests spanning different banks of the memory device. In each memory controller cycle, selection logic may select both a row request and a column request (relating to a different bank than the row request) for issuing to the memory device based on a set of timing status bits. Following issuance of requests, the memory controller updates the queue to maintain the queued requests in a time-ordered, compressed sequence. The memory controller furthermore updates the timing status bits that are used by the selection logic to select requests from the queue based on a history of past memory requests.
1 . A method for queuing memory operation requests, the method comprising:
storing a queue of memory operation requests ordered based on relative times of receipt in a fixed set of ordered request slots, the memory operation requests associated with multiple different memory banks of a memory device, wherein at least one of the ordered request slots stores a request pair including both a first row request for activating a row of a first bank and a corresponding first column request for performing a read or write for the row of the first bank;
storing a new request in an input register;
selecting, in a given memory controller cycle based on ordering constraints and relative positions of the memory operation requests in the fixed set of ordered request slots indicating the relative times of receipt, the first row request for activating the row of the first bank, and concurrently selecting a second column request for issuing to a second bank separate from the first bank, wherein the first row request and the second column request are selected in the same memory controller cycle;
updating the queue to remove the second column request from the queue and to shift at least a subset of remaining requests between the ordered request slots such that a slot vacated by the second column request is filled and a slot corresponding to the request pair remains filled by the first column request, and to add the new request from the input register to the ordered request slots adjacent to the shifted subset of remaining requests in the queue, wherein the requests are maintained in the queue in time order and positioned in a compressed set of adjacent slots of the fixed set of ordered request slots; and
issuing the first row request and the second column request from an output register to the first and second banks of the memory device during the same memory controller cycle.
2 . The method of claim 1 , wherein updating the queue comprises:
shifting a block of requests in the queue that are newer than the second column request to fill the one or more slots vacated by the second column request; and
shift in the new request to a vacated slot at a top of the block.
3 . The method of claim 1 , wherein updating the queue comprises:
determining if the second column request is completed; and
updating the queue in response to determining that the second column request is completed.
4 . The method of claim 1 , wherein selecting the first row request and the second column request comprises:
identifying the first row request and the second column request as oldest requests in the queue that can be issued to the memory device in a current memory controller cycle.
5 . The method of claim 1 , wherein selecting the first row request and the second column request comprises:
identifying the first row request and the second column request as oldest requests in the queue that have reached an age timeout.
6 . The method of claim 1 , wherein selecting the second column request comprises:
determining a type of an immediately prior issued request as either a read request or a write request; and
identifying the second column request as a request that is of a same type as the prior issued request.
7 . The method of claim 1 , further comprising:
shifting a bank address and request type associated with the issued request into a post-issue shift register;
selecting one or more taps from the post-issue shift register based on control inputs; and
decoding the one or more taps to update status bits representing the ordering constraints.
8 . The method of claim 1 , wherein selecting the first row request and the second column request comprises:
performing comparisons for each request in the queue, an address of the request in the queue with an address of the first row request and the second column request being removed from the queue and an address of the new request being added to the queue, to update status bits representing the ordering constraints based on the comparisons, and to select the first row request and the second column request based on the status bits.
9 . The method of claim 1 , further comprising:
receiving a memory request;
identifying that the memory request includes operations associated with multiple different banks of the memory device; and
dividing the memory request into a set of multiple requests in which each of the multiple requests requires access to only a single bank.
10 . A memory controller for queuing memory operation requests, the memory controller comprising:
a queue to store memory operation requests ordered based on relative times of receipt in a fixed set of ordered request slots, the memory operation requests associated with multiple different memory banks of a memory device, wherein at least one of the ordered request slots stores a request pair including both a first row request for activating a row of a first bank and a corresponding first column request for performing a read or write for the row of the first bank;
an input register to store a new request;
request selection logic to select, in a given memory controller cycle based on ordering constraints and relative positions of the memory operation requests in the fixed set of ordered request slots indicating the relative times of receipt, the first row request for activating the row of the first bank, and concurrently selecting a second column request for issuing to a second bank separate from the first bank, wherein the first row request and the second column request are selected in the same memory controller cycle;
queue update logic to update the queue to remove the second column request from the queue and to shift at least a subset of remaining requests between the ordered request slots such that a slot vacated by the second column request is filled and a slot corresponding to the request pair remains filled by the first column request, and to add the new request from the input register to the ordered request slots adjacent to the shifted subset of remaining requests in the queue, wherein the requests are maintained in the queue in time order and positioned in a compressed set of adjacent slots of the fixed set of ordered request slots; and
an output register to receive the first row request and the second column request, and to issue the first row request and the second column request to separate banks of the memory device during the same memory controller cycle.
11 . The memory controller of claim 10 , wherein the queue update logic is configured to shift a block of requests in the queue that are newer than the second column request to fill the one or more slots vacated by the second column request, and to shift in the new request to a vacated slot at a top of the block.
12 . The memory controller of claim 10 , wherein the queue update logic is configured to determine if the second column request is completed, and update the queue in response to determining that the second column request is completed.
13 . The memory controller of claim 10 , wherein the request selection logic is configured to identify the first row request and the second column request as oldest requests in the queue that can be issued to the memory device in a current memory controller cycle.
14 . The memory controller of claim 10 , wherein the request selection logic is configured to identify the first row request and the second column request as oldest requests in the queue that have reached an age timeout.
15 . The memory controller of claim 10 , wherein the request selection logic is configured to determine a type of an immediately prior issued column request as either a read request or a write request, and identify the second column request as a request that is of a same type as the prior issued request.
16 . The memory controller of claim 15 , further comprising post-issue logic including:
a post-issue shift register to shift in a bank address and request type associated with the issued request;
a multiplexer to select one or more taps of the post-issue shift register based on control inputs; and
decoding logic to decode the one or more taps to update status bits representing the ordering constraints.
17 . The memory controller of claim 10 , wherein the request selection logic includes:
comparator logic to perform comparisons for each request in the queue, an address of the request in the queue with an address of the first row request and the second column request being removed from the queue, to compare the address of the request in the queue to an address of the new request being added to the queue, and to update status bits representing the ordering constraints based on the comparisons; and
selection logic to select the first row request and the second column request based on the status bits.
18 . A memory system comprising:
a memory device; and
a memory controller for queuing memory operation requests, the memory controller comprising:
a queue to store memory operation requests ordered based on relative times of receipt in a fixed set of ordered request slots, the memory operation requests associated with multiple different memory banks of a memory device, wherein at least one of the ordered request slots stores a request pair including both a first row request for activating a row of a first bank and a corresponding first column request for performing a read or write for the row of the first bank;
an input register to store a new request;
request selection logic to select, in a given memory controller cycle based on ordering constraints and relative positions of the memory operation requests in the fixed set of ordered request slots indicating the relative times of receipt, the first row request for activating the row of the first bank, and concurrently selecting a second column request for issuing to a second bank separate from the first bank, wherein the first row request and the second column request are selected in the same memory controller cycle;
queue update logic to update the queue to remove the second column request from the queue and to shift at least a subset of remaining requests between the ordered request slots such that a slot vacated by the second column request is filled and a slot corresponding to the request pair remains filled by the first column request, and to add the new request from the input register to the ordered request slots adjacent to the shifted subset of remaining requests in the queue, wherein the requests are maintained in the queue in time order and positioned in a compressed set of adjacent slots of the fixed set of ordered request slots; and
an output register to receive the first row request and the second column request, and to issue the first row request and the second column request to separate banks of the memory device during the same memory controller cycle.
19 . The memory system of claim 18 , wherein the queue update logic is configured to shift a block of requests in the queue that are newer than the first row request and the second column request to fill the one or more slots vacated by the first row request and the second column request, and to shift in the new request to a vacated slot at a top of the block.
20 . The memory system of claim 18 , wherein the queue update logic is configured to determine if the first row request and the second column request are completed, and update the queue in response to determining that the first row request and the second column request are completed.