Method and apparatus for command processing in a multi-processor environment
A command is received at a first processor from a system component. The first processor instructs an available second processor to perform part of the command. The second processor constructs, based on the instruction, a hardware accelerator command and executes the hardware accelerator command using a hardware accelerator. The second processor then provides a result from the hardware accelerator to the first processor.
1 . A storage drive comprising:
a first processor configured to receive a command from one or more system components of the storage drive; and
one or more second processors configured to
receive an instruction from the first processor to perform part of the command, construct, based on the instruction, a hardware accelerator command,
execute the hardware accelerator command using a hardware accelerator, and provide a result from the hardware accelerator to the first processor,
wherein
the one or more second processors are configured to i) determine which one or more of a plurality of hardware accelerators are available to execute the part of the command, and ii) execute the hardware accelerator command using the one or more of the plurality of hardware accelerators, and
the one or more of the plurality of hardware accelerators is more specialized for executing the part of the command than another one or more of the plurality of hardware accelerators.
2 . The storage drive of claim 1 , wherein each respective second processor of the one or more second processors is configured to communicate with a respective hardware accelerator, and wherein the first processor is further configured to:
identify the hardware accelerator associated with the part of the command; and
transmit the instruction to a respective one of the one or more second processors configured to communicate with the identified hardware accelerator.
3 . The storage drive of claim 1 , further comprising an inter-processor switch configured to enable communication between the first processor and the one or more second processors.
4 . The storage drive of claim 3 , wherein the first processor is further configured to:
generate an inter-processor packet for communication with the one or more second processors; and
transmit the inter-processor packet to the inter-processor switch.
5 . The storage drive of claim 3 , wherein each second processor of the one or more second processors is configured to:
generate an inter-processor packet for communication with the first processor; and
transmit the inter-processor packet to the inter-processor switch.
6 . The storage drive of claim 1 , wherein each second processor of the one or more second processors is further configured to execute the part of the command in fewer clock cycles than the first processor.
7 . The storage drive of claim 1 , wherein the first processor further comprises:
a launcher configured to receive an inter-processor packet; and
a core configured to receive a command based on the inter-processor packet.
8 . The storage drive of claim 1 , wherein each second processor of the one or more second processors further comprises:
a core configured to
receive a command based on an inter-processor packet,
generate an external interaction packet, and
transmit the external interaction packet to a hardware accelerator; and
a launcher configured to
receive the inter-processor packet, and
receive, from the hardware accelerator, a status of the hardware accelerator.
9 . The storage drive of claim 1 , wherein the first processor is configured to initiate processing via the hardware accelerator by generating an instruction to offload processing of the part of the command to the one or more second processors and concurrently with the processing of the part of the command by the hardware accelerator processing another command at the first processor.
10 . A method comprising:
receiving, at a first processor of a storage drive, a command from one or more system components;
receiving, at a second processor of a plurality of second processors of the storage drive, an instruction from the first processor to perform a part of the command;
constructing, based on the instruction, a hardware accelerator command;
executing, at the second processor, the hardware accelerator command using a first hardware accelerator;
providing a result from the first hardware accelerator to the first processor;
receiving, at the second processor, an inter-processor packet;
receiving, at the second processor, a command based on the inter-processor packet;
generating, at the second processor, an external interaction packet;
transmitting, by the second processor, the external interaction packet to a second hardware accelerator; and
receiving, at the second processor, from the second hardware accelerator, a status of the second hardware accelerator.
11 . The method of claim 10 , wherein each respective second processor of the plurality of second processors is configured to communicate with a respective hardware accelerator, the method further comprising:
identifying, at the first processor, the first hardware accelerator associated with the part of the command; and
transmitting the instruction from the first processor to a respective one of the plurality of second processors configured to communicate with the identified first hardware accelerator.
12 . The method of claim 10 , further comprising enabling communication between the first processor and the plurality of second processors using an inter-processor switch.
13 . The method of claim 12 , further comprising:
generating, at the first processor, an inter-processor packet for communication with the plurality of second processors; and
transmitting, by the first processor, the inter-processor packet for communication with the first processor to the inter-processor switch.
14 . The method of claim 12 , further comprising:
generating, at the second processor, an inter-processor packet for communication with the first processor; and
transmitting, by the second processor, the inter-processor packet for communication with the processor to the inter-processor switch.
15 . The method of claim 10 , further comprising executing, by the second processor, the part of the command in fewer clock cycles than the first processor.
16 . The method of claim 10 , further comprising:
receiving, at the first processor, an inter-processor packet; and
receiving, at the first processor, a command based on the inter-processor packet received at the first processor.
17 . A non-transitory, computer-readable medium having non-transitory computer-readable instructions encoded thereon for execution by a processor, the non-transitory computer-readable instructions comprising:
an instruction to receive, at a first processor of a storage drive, a command from one or more system components;
an instruction to receive, at a second processor of a plurality of second processors of the storage drive, an instruction from the first processor to perform part of the command;
an instruction to construct, based on the instruction, a hardware accelerator command;
an instruction to execute, at the second processor, the hardware accelerator command using a first hardware accelerator associated with the command;
an instruction to provide a result from the first hardware accelerator to the first processor;
an instruction to receive, at the second processor, an inter-processor packet;
an instruction to receive, at the second processor, a command based on the inter-processor packet;
an instruction to generate, at the second processor, an external interaction packet;
an instruction to transmit, by the second processor, the external interaction packet to a second hardware accelerator; and
an instruction to receive, at the second processor, from the second hardware accelerator, a status of the second hardware accelerator.
18 . The non-transitory, computer-readable medium of claim 17 , further comprising:
instructions for each respective second processor of the plurality of second processors to communicate with a respective hardware accelerator;
an instruction to identify, at the first processor, the first hardware accelerator associated with the part of the command; and
an instruction to transmit the command from the first processor to a respective one of the plurality of second processors configured to communicate with the identified first hardware accelerator.
19 . The non-transitory, computer-readable medium of claim 17 , wherein the non-transitory computer-readable instructions that are encoded further comprise an instruction to enable communication between the first processor and the plurality of second processors using an inter-processor switch.
20 . The non-transitory, computer-readable medium of claim 19 , wherein the non-transitory computer-readable instructions that are encoded further comprise:
an instruction to generate, at the first processor, an inter-processor packet for communication with the plurality of second processors; and
an instruction to transmit, by the first processor, the inter-processor packet to the inter-processor switch.
21 . The non-transitory, computer-readable medium of claim 19 , wherein the non-transitory computer-readable instructions that are encoded further comprise:
an instruction to generate, at the second processor, an inter-processor packet for communication with the first processor; and
an instruction to transmit, by the second processor, the inter-processor packet to the inter-processor switch.
22 . The non-transitory, computer-readable medium of claim 17 , wherein the non-transitory computer-readable instructions that are encoded further comprise an instruction to execute, by the second processor, the part of the command in fewer clock cycles than the first processor.
23 . The non-transitory, computer-readable medium of claim 17 , wherein the non-transitory computer-readable instructions that are encoded further comprise:
an instruction to receive, at the first processor, an inter-processor packet; and
an instruction to receive, at the first processor, a command based on the inter-processor packet.
24 . A storage drive comprising:
a first processor configured to receive a command from one or more system components of the storage drive;
one or more second processors configured to
receive an instruction from the first processor to perform part of the command,
construct, based on the instruction, a hardware accelerator command,
execute the hardware accelerator command using a hardware accelerator, and
provide a result from the hardware accelerator to the first processor; and
a programmable accelerator, wherein
the first processor is implemented as a general processing element of the programmable accelerator, and
the one or more second processors is implemented as a task specific processing element of the programmable accelerator.
25 . A storage drive comprising:
a first processor configured to receive a command from one or more system components of the storage drive; and
one or more second processors configured to
receive an instruction from the first processor to perform part of the command,
construct, based on the instruction, a hardware accelerator command,
execute the hardware accelerator command using a hardware accelerator, and
provide a result from the hardware accelerator to the first processor,
wherein the first processor is configured to i) determine which one of the one or more second processors is available to communicate with the hardware accelerator to execute the part of the command, ii) send the command to the one of the one or more second processors that is available to communicate with the hardware accelerator, and iii) not send the command to another one of the of the one or more second processors not available to communicate with the hardware accelerator.
26 . A storage drive comprising:
a first processor configured to receive a command from one or more system components of the storage drive;
one or more second processors configured to
receive an instruction from the first processor to perform part of the command,
construct, based on the instruction, a hardware accelerator command,
execute the hardware accelerator command using a hardware accelerator, and
provide a result from the hardware accelerator to the first processor;
a host controller configured to receive the command from a processor of a host device separate from the storage drive; and
a launcher configured to receive the command from the host controller, generate an inter-processor interaction packet in response to receiving the command, and either forward the inter-processor interaction packet to the first processor or to a switch.
27 . The storage drive of claim 26 , wherein the first processor is configured, based on information in the inter-processor interaction packet, to load an internal program counter and a command index, and, based on the command index, to access command information associated with the inter-processor interaction packet.
28 . The storage drive of claim 26 , further comprising the switch configured to forward the inter-processor interaction packet to the first processor or the one or more second processors.
29 . The storage drive of claim 28 , wherein the inter-processor interaction packet includes information indicating a next processor to continue processing the command after the hardware accelerator completes processing of the part of the command.
30 . The storage drive of claim 28 , further comprising memory configured to store host command information and instructions associated with the inter-processor interaction packet,
wherein the one or more second processors is configured to load a command index according to the inter-processor interaction packet and, based on the command index, to access the host command information stored in memory and execute the instructions from the memory.