Mark-live instruction that sets discard-eligibility metadata in cache lines for use by mark-dead events
An apparatus comprises instruction decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. Cache control circuitry is configured to set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty. In response to a mark-dead event associated with a given cache line, the cache control circuitry determines depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.
1 . An apparatus comprising:
instruction decoding circuitry configured to decode instructions;
processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry; and
cache control circuitry configured to:
set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty; and
in response to a mark-dead event associated with a given cache line, determine depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.
2 . The apparatus according to claim 1 , in which, in response to the mark-live instruction, for a given target cache line identified based on the mark-live target address information which is not already cached in a designated level of cache designated to be allocated with the given target cache line, the cache control circuitry is configured to allocate the given target cache line to the designated level of cache specifying a predetermined value as cached data for the given target cache line, and set the discard-eligibility metadata for the given target cache line to indicate that the given target cache line is eligible for being treated as a discardable cache line.
3 . The apparatus according to claim 2 , in which the cache control circuitry is configured to generate the predetermined value as the cached data, without issuing a linefill request to obtain the cached data specifying the predetermined value from a further cache or memory.
4 . The apparatus according to claim 2 , in which the cache control circuitry is configured to allocate the given target cache line specifying the predetermined value to the given cache in a dirty-but-discardable state indicating that the given target cache line is dirty and is currently treated as a discardable cache line.
5 . The apparatus according to claim 2 , in which in response to the mark-live instruction, when the given target cache line is already cached in the designated level of cache in a clean state, the cache control circuitry is configured to retain the given target cache line in the designated level of cache in the clean state with the discard-eligibility metadata for the given target cache line set to indicate that the given target cache line is eligible for being treated as a discardable cache line.
6 . The apparatus according to claim 2 , in which in response to the mark-live instruction, the cache control circuitry is configured to set cached data held by the designated level of cache for the given target cache line to the predetermined value regardless of a previous coherency state in which the given target cache line is held in the designated level of cache.
7 . The apparatus according to claim 1 , in which the cache control circuitry is configured to identify, as the one or more target cache lines, one or more cache lines which are entirely within an address range identified based on the mark-live target address information.
8 . The apparatus according to claim 7 , in which the address range is defined by a range start address and a range end parameter, the mark-live instruction identifying at least the range start address as an operand of the make-live instruction.
9 . The apparatus according to claim 1 , in which, in response to the mark-dead event associated with mark-dead target address information, the cache control circuitry is configured to treat as a discardable cache line one or more cache lines corresponding to the mark-dead target address information which are indicated by the discard-eligibility metadata as being eligible for being treated as the discardable cache line.
10 . The apparatus according to claim 9 , in which, in response to the mark-dead event, for a given cache line corresponding to the mark-dead target address information which is indicated by the discard-eligibility metadata as being ineligible for being treated as the discardable cache line, the cache control circuitry is configured to prevent the given cache line being treated as a discardable cache line.
11 . The apparatus according to claim 9 , in which the cache control circuitry is configured to treat a given cache line as the discardable cache line by setting discard-indicating metadata for the given cache line indicating that the given cache line is discardable on eviction without data writeback even if the given cache line is dirty.
12 . The apparatus according to claim 11 , in which the cache control circuitry is configured to clear the discard-indicating metadata for the given cache line in response to detecting a read, write or snoop request to the given cache line.
13 . The apparatus according to claim 1 , in which the mark-dead event comprises execution of a mark-dead instruction specifying the mark-dead target address information.
14 . The apparatus according to claim 1 , in which the mark-dead event comprises receipt, from an interconnect, of a mark-dead event request specifying the mark-dead target address information.
15 . The apparatus according to claim 1 , in which, for at least one setting of the apparatus, the discard-eligibility metadata is allowed to be updated in response to a mark-live instruction executed in a least privileged execution state.
16 . A system comprising:
the apparatus of claim 1 , implemented in at least one packaged chip;
at least one system component; and
a board,
wherein the at least one packaged chip and the at least one system component are assembled on the board.
17 . A chip-containing product comprising the system of claim 16 , wherein the system is assembled on a further board with at least one other product component.
18 . A non-transitory storage medium storing computer-readable code for fabrication of an apparatus according to claim 1 .
19 . A method comprising:
decoding instructions;
performing data processing in response to the decoded instructions; and
in response to decoding a mark-live instruction specifying mark-live target address information, setting discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty; and
in response to a mark-dead event associated with a given cache line, determining depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.
20 . A non-transitory storage medium storing a computer program comprising instructions which, when executed by a host data processing apparatus, control the host data processing apparatus to provide an instruction execution environment for execution of target code, the computer program comprising:
instruction decoding program logic configured to decode instructions of the target code;
processing program logic configured to control the host data processing apparatus to perform data processing in response to the instructions decoded by the instruction decoding program logic; and
cache control program logic configured to:
set, in response to decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty; and
in response to a mark-dead event associated with a given cache line, determine depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.