IP Library Granted Patent US 12699568
Granted Patent B2
US 12699568 · App. 18/639,815 · Granted Aug 4, 2026

Runtime adaptive prefetching in a many-core system

Inventors: Erika Susana Alcorta Lozano (Austin, TX); Mahesh Jagdish Madhav (Portland, OR); Raymond Scott Tetrick (Portland, OR)
Assignee: Ampere Computing LLC
G06F9/3802G06F12/0862G06F2212/6024G06F2212/6028
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Quick Facts
Patent No.
US 12699568
App. No.
18/639,815
Granted
Aug 4, 2026
Kind
B2
Abstract

Disclosed are techniques for runtime adaptive prefetching in a many-core system. In an aspect, a method for runtime adaptive prefetching in a many-core system may include periodically performing the following steps: determining, for a first processor core in a many-core system, a workload classification based on at least one performance indicator of the first processor core; determining a first prefetching configuration from a plurality of prefetching configurations based on the workload classification; and configuring at least the first processor core according to the first prefetching configuration.

Claims (51)

1 . A method for runtime adaptive prefetching in a many-core system, the method comprising:

periodically performing a prefetch configuration operation comprising:

determining, for a first processor core in a many-core system, a workload classification based on at least one performance indicator of the first processor core;

determining a prefetching configuration from a plurality of prefetching configurations based on the workload classification, wherein each prefetching configuration in the plurality of prefetching configurations specifies an enabled or disabled state for each of a plurality of prefetching algorithms; and

configuring at least the first processor core according to the prefetching configuration,

wherein each processor core in the many-core system can be configured in the plurality of prefetching configurations, wherein the plurality of prefetching configurations includes a first prefetching configuration in which none of the plurality of prefetching algorithms is active, a second prefetching configuration in which one of the plurality of prefetching algorithms is active, and a third prefetching configuration in which more than one of the plurality of prefetching algorithms is active simultaneously.

2 . The method of claim 1 , wherein determining the workload classification based on at least one performance indicator of the first processor core comprises determining the workload classification based on at least one hardware counter value.

3 . The method of claim 1 , wherein determining the workload classification based on at least one performance indicator of the first processor core comprises determining the workload classification based on at least one of:

a count of instructions per cycle (IPC);

a count of memory accesses;

a count of branch hits or misses;

a count of translation look-aside buffer (TLB) hits or misses;

a count of cache hits or misses;

a ratio of cache misses to memory accesses;

a ratio of L2 data cache refills to cache misses; or

a ratio of L2 instruction cache refills to branch misses.

4 . The method of claim 1 , wherein determining the workload classification based on at least one performance indicator of the first processor core and determining the prefetching configuration from the plurality of prefetching configurations based on the workload classification comprises:

providing at least one performance indicator to a trained machine learning (ML) model instantiated in hardware, a firmware layer, an operating system layer, an application layer, or a combination thereof; and

receiving, from the ML model, the determined prefetching configuration.

5 . The method of claim 4 , wherein the ML model comprises a decision tree, a neural network, a Vowpal's wabbit, a contextual bandit, a Bayes classifier, a linear classifier, a component analyzer, a transformer, or a combination thereof.

6 . The method of claim 4 , further comprising training the ML model prior to its use.

7 . The method of claim 1 , wherein configuring at least the first processor core according to the prefetching configuration comprises writing register settings to at least one control register of the first processor core.

8 . The method of claim 7 , wherein configuring at least the first processor core according to the prefetching configuration comprises writing register settings to at least one control register of at least one other processor core in the many-core system.

9 . The method of claim 1 , further comprising periodically performing the prefetch configuration operation for at least one other processor core in the many-core system.

10 . An apparatus for runtime adaptive prefetching in a many-core system, the apparatus comprising:

a plurality of processor cores;

control circuitry for performing a control function; and

a mesh interconnect communicatively coupled to the plurality of processor cores and the control circuitry;

wherein the control circuitry is configured to periodically perform a prefetch configuration operation comprising:

determining, for a first processor core in a many-core system, a workload classification based on at least one performance indicator of the first processor core;

determining a prefetching configuration from a plurality of prefetching configurations based on the workload classification, wherein each prefetching configuration in the plurality of prefetching configurations specifies an enabled or disabled state for each of a plurality of prefetching algorithms; and

configuring at least the first processor core according to the prefetching configuration,

wherein each processor core in the many-core system can be configured in the plurality of prefetching configurations, wherein the plurality of prefetching configurations includes a first prefetching configuration in which none of the plurality of prefetching algorithms is active, a second prefetching configuration in which one of the plurality of prefetching algorithms is active, and a third prefetching configuration in which more than one of the plurality of prefetching algorithms is active simultaneously.

11 . The apparatus of claim 10 , wherein, to determine the workload classification based on at least one performance indicator of the first processor core, the control circuitry is configured to determine the workload classification based on at least one hardware counter value.

12 . The apparatus of claim 10 , wherein, to determine the workload classification based on at least one performance indicator of the first processor core, the control circuitry is configured to determine the workload classification based on at least one of:

a count of instructions per cycle (IPC);

a count of memory accesses;

a count of branch hits or misses;

a count of translation look-aside buffer (TLB) hits or misses;

a count of cache hits or misses;

a ratio of cache misses to memory accesses;

a ratio of L2 data cache refills to cache misses; or

a ratio of L2 instruction cache refills to branch misses.

13 . The apparatus of claim 10 ,

wherein the control circuitry comprises a trained machine learning (ML) model instantiated in hardware, a firmware layer, an operating system layer, an application layer, or a combination thereof, and

wherein, to determine the workload classification based on at least one performance indicator of the first processor core and to determine the prefetching configuration from the plurality of prefetching configurations based on the workload classification, the control circuitry is configured to provide at least one performance indicator to the ML model and to receive the determined prefetching configuration from the ML model.

14 . The apparatus of claim 13 , wherein the ML model comprises a decision tree, a neural network, a Vowpal's wabbit, a contextual bandit, a Bayes classifier, a linear classifier, a component analyzer, a transformer, or a combination thereof.

15 . The apparatus of claim 13 , wherein the ML model is trained prior to its use.

16 . The apparatus of claim 10 , wherein, to configure at least the first processor core according to the prefetching configuration, the control circuitry is configured to write register settings to at least one control register of the first processor core.

17 . The apparatus of claim 16 , wherein, to configure at least the first processor core according to the prefetching configuration, the control circuitry is configured to write register settings to at least one control register of at least one other processor core in the many-core system.

18 . The apparatus of claim 10 , wherein the control circuitry is further configured to periodically perform the prefetch configuration operation for at least one other processor core in the many-core system.