Self-provisioning and flexible hardware accelerator architecture
A hardware (HW) accelerator architecture is described that adapts to a number of post-quantum cryptography (PQC) algorithms. The architecture determines whether to re-provision memory that stores constants values for arithmetic computations used for executed PQC algorithms. The architecture enables only a single set of constants to be stored at any particular time and the memory only needs to have a capacity to ensure that the largest set of constants among one of several PQC algorithms is stored while obviating the need to store the constants used across all PQC algorithms.
1 . A hardware accelerator, comprising:
a memory;
control logic configured to:
receive control parameters associated with an executed one of a plurality of cryptographic algorithms, each one of the plurality of cryptographic algorithms executing a respective arithmetic computation on a respective data set; and
selectively cause initial data values stored in the memory to be overwritten with updated data values based upon a determination of whether the received control parameters match previously-received control parameters that are associated with the initial data values stored in the memory; and
an arithmetic logic unit (ALU) configured to execute the respective arithmetic computation, which is associated with the executed one of the plurality of cryptographic algorithms, on the respective data set using the initial data values or the updated data values.
2 . The hardware accelerator of claim 1 , wherein the control logic is configured to cause the initial data values stored in the memory to be overwritten with the updated data values when the received control parameters do not match the previously-received control parameters.
3 . The hardware accelerator of claim 1 , wherein the control logic is configured to retain the initial data values stored in the memory to not be overwritten with the updated data values when the received control parameters match the previously-received control parameters.
4 . The hardware accelerator of claim 1 , wherein the received control parameters match the previously-received control parameters when the received control parameters and the previously-received control parameters are associated with the same cryptographic algorithm from among the plurality of cryptographic algorithms.
5 . The hardware accelerator of claim 1 , wherein the control logic is configured to receive a request for overwriting the initial data values stored in the memory with the updated data values, and
wherein the control logic is configured to cause the initial data values stored in the memory to be overwritten with the updated data values based upon the request.
6 . The hardware accelerator of claim 1 , wherein the respective arithmetic computation, which is associated with the executed one of the plurality of cryptographic algorithms and performed on the respective data set, comprises a Number Theoretic Transform (NTT) operation or an inverse NTT (I-NTT) operation.
7 . The hardware accelerator of claim 1 , wherein the initial data values stored in the memory comprise first constants values corresponding to the previously-received control parameters, which are used in accordance with a first Number Theoretic Transform (NTT) operation or a first inverse NTT (I-NTT) operation, and
wherein the updated data values selectively stored in the memory comprise second constants values corresponding to the received control parameters, which are used in accordance with a second NTT operation or a second I-NTT operation.
8 . The hardware accelerator of claim 1 , wherein each one of the plurality of cryptographic algorithms utilizes a respective set of constants values corresponding to a Number Theoretic Transform (NTT) operation or an inverse NTT (I-NTT) operation, and
wherein the memory has a storage capacity configured to store a largest set of constants values from among the respective sets of constants values utilized by the plurality of cryptographic algorithms, but less than a total sum of the respective sets of constants values utilized by all of the plurality of cryptographic algorithms.
9 . The hardware accelerator of claim 1 , wherein the memory comprises:
a constants memory configured to store constants values corresponding to a Number Theoretic Transform (NTT) operation or an inverse NTT (I-NTT) operation corresponding to the respective arithmetic computation that is associated with the executed one of the plurality of cryptographic algorithms; and
a data memory configured to store the respective data set and an output of the respective arithmetic computation, which is associated with the executed one of the plurality of cryptographic algorithms, on the respective data set performed via the ALU.
10 . The hardware accelerator of claim 9 , wherein the control logic is configured to selectively cause, based upon the received control parameters, a portion of the updated data values to be further stored in the data memory.
11 . The hardware accelerator of claim 1 , wherein the control logic is configured to selectively cause the initial data values stored in the memory to be overwritten with the updated data values independently of software processes, and the ALU is configured to perform the respective arithmetic computation, which is associated with the executed one of the plurality of cryptographic algorithms, on the respective data set using the initial data values or the updated data values independently of software processes.
12 . The hardware accelerator of claim 1 , wherein the control logic is configured, when the initial data values stored in the memory are overwritten with updated data values, to cause the memory to store (i) the updated data values, and (ii) the respective data set upon which the respective arithmetic computation is executed by the ALU in accordance with the executed one of the plurality of cryptographic algorithms.
13 . A computer-implemented method, comprising:
receiving control parameters associated with an executed one of a plurality of cryptographic algorithms, each one of the plurality of cryptographic algorithms executing a respective arithmetic computation on a respective data set; determining whether the received control parameters, which are associated with updated data values, match previously-received control parameters that are associated with initial data values stored in a memory;
selectively overwriting the initial data values stored in the memory with the updated data values based upon whether the received control parameters match the previously-received control parameters that are associated with the initial data values stored in the memory; and
executing the respective arithmetic computation, which is associated with the executed one of the plurality of cryptographic algorithms, on the respective data set using the initial data values or the updated data values.
14 . The computer-implemented method of claim 13 , wherein the selectively overwriting the initial data values stored in the memory with the updated data values comprises overwriting the initial data values stored in the memory with the updated data values when the received control parameters do not match the previously-received control parameters.
15 . The computer-implemented method of claim 13 , wherein the selectively overwriting the initial data values stored in the memory with the updated data values comprises retaining the initial data values stored in the memory and not overwriting the initial data values when the received control parameters match the previously-received control parameters.
16 . The computer-implemented method of claim 13 , wherein the received control parameters match the previously-received control parameters when the received control parameters and the previously-received control parameters are associated with the same cryptographic algorithm from among the plurality of cryptographic algorithms.
17 . The computer-implemented method of claim 13 , further comprising:
receiving a request for overwriting the initial data values stored in the memory with the updated data values; and
overwriting the initial data values stored in the memory with the updated data values based upon the request.
18 . The computer-implemented method of claim 13 , wherein the initial data values stored in the memory comprise first constants values corresponding to the previously-received control parameters, which are used in accordance with a first Number Theoretic Transform (NTT) operation or a first inverse NTT (I-NTT) operation, and
wherein the updated data values selectively stored in the memory comprise second constants values corresponding to the received control parameters, which are used in accordance with a second NTT operation or a second I-NTT operation.
19 . The computer-implemented method of claim 13 , wherein each one of the plurality of cryptographic algorithms utilizes a respective set of constants values corresponding to a Number Theoretic Transform (NTT) operation or an inverse NTT (I-NTT) operation, and
wherein the memory has a storage capacity configured to store a largest set of constants values from among the respective sets of constants values utilized by the plurality of cryptographic algorithms, but less than a total sum of the respective sets of constants values utilized by all of the plurality of cryptographic algorithms.
20 . The computer-implemented method of claim 13 , wherein the memory comprises a constants memory configured to store the constants values corresponding to a Number Theoretic Transform (NTT) operation or an inverse NTT (I-NTT) operation corresponding to the respective arithmetic computation that is associated with the executed one of the plurality of cryptographic algorithms, and further comprising:
storing, via a data memory, the respective data set and an output of the respective arithmetic computation, which is associated with the executed one of the plurality of cryptographic algorithms, on the respective data set.
21 . The computer-implemented method of claim 20 , further comprising:
selectively causing, based upon the received control parameters, the data memory to further store a portion of the updated data values.
22 . The computer-implemented method of claim 13 , further comprising:
when the initial data values stored in the memory are overwritten with updated data values, storing, (i) the updated data values, and (ii) the respective data set upon which the respective arithmetic computation is executed in accordance with the executed one of the plurality of cryptographic algorithms.