Network functions virtualization platforms with function chaining capabilities
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.
1 . An integrated circuit configurable to communicatively couple to a host processor separate from the integrated circuit, the integrated circuit comprising:
a first virtual function hardware accelerator configurable to perform a first function;
a second virtual function hardware accelerator configurable to perform a second function; and
data switching circuitry configurable to:
receive first data output from the host processor, the host processor configurable to retrieve the first data from host processor memory separate from the host processor and the integrated circuit;
send the first data to the first virtual function hardware accelerator to perform the first function on the first data to generate second data;
send the second data to the host processor configurable to store the second data at the host processor memory; and
send the second data to the second virtual function hardware accelerator to perform the second function on the second data to generate third data.
2 . The integrated circuit of claim 1 , wherein the data switching circuitry is configurable to:
send the third data to a third virtual function hardware accelerator to perform a third function on the third data to produce a fourth data based on the third data being characterized by a first data type.
3 . The integrated circuit of claim 2 , wherein the first data type corresponds to a data type descriptor comprising one or more chaining instructions, and wherein the data switching circuitry is configurable to send the third data to the third virtual function hardware accelerator based on the one or more chaining instructions.
4 . The integrated circuit of claim 2 , wherein the second data respectively corresponds to a second data type different from the first data type, and wherein the data switching circuitry is configurable to determine to send the second data to the host processor based on the second data type.
5 . The integrated circuit of claim 3 , wherein the data switching circuitry is configurable to transmit the fourth data and resulting data to one or more chained virtual function hardware accelerators based on the one or more chaining instructions.
6 . The integrated circuit of claim 1 , wherein the second function performed by the second virtual function hardware accelerator is different from the first function performed by the first virtual function hardware accelerator.
7 . The integrated circuit of claim 1 , comprising a direct memory access engine configurable to transmit the third data to a respective virtual machine of a plurality of virtual machines configurable to run on the host processor that is coupled to the integrated circuit.
8 . The integrated circuit of claim 7 , wherein the first virtual function hardware accelerator and the second virtual function hardware accelerator respectively correspond to programmable logic, and wherein the first virtual function hardware accelerator and the second virtual function hardware accelerator are configurable to perform different functions.
9 . A method, comprising:
receiving, via a coprocessor, first data from a host processor separate from the coprocessor, the host processor configurable to retrieve the first data from host processor memory separate from the host processor and the coprocessor;
using a first virtual function accelerator in the coprocessor to perform a first function on the first data to produce second data;
outputting the second data to the host processor from the coprocessor configurable to store the second data at the host processor memory; and
using a second virtual function accelerator in the coprocessor to perform a second function on the second data to produce third data.
10 . The method of claim 9 , comprising:
determining to use a third virtual function accelerator in the coprocessor to perform a third function on the third data based on a route identifier of the third data, the route identifier indicative of one or more chaining instructions for the third data.
11 . The method of claim 10 , comprising:
using the third virtual function accelerator in the coprocessor to perform the third function on the third data to produce fourth data based on the one or more chaining instructions.
12 . The method of claim 9 , wherein the second function performed by the second virtual function accelerator is different from the first function performed by the first virtual function accelerator.
13 . The method of claim 9 , comprising using data switching circuitry to transmit the third data and resulting data among a plurality of virtual function accelerators according to one or more chaining instructions.
14 . The method of claim 13 , wherein the plurality of virtual function accelerators comprises the first virtual function accelerator, the second virtual function accelerator, or both.
15 . A system, comprising:
a host processor configurable to retrieve first data from host processor memory separate from the host processor and output the first data; and
a programmable logic device separate from the host processor, the programmable logic device communicatively coupled to the host processor and comprising programmable logic configurable to implement:
a first virtual function accelerator configurable to generate second data based on performing a first function on the first data and to output the second data to the host processor; and
a second virtual function accelerator configurable to generate third data based on performing a second function on the second data.
16 . The system of claim 15 , wherein the programmable logic device comprises a plurality of virtual function accelerators that includes the second virtual function accelerator, and wherein the first function performed by the first virtual function accelerator is a different function than functions respectively performed by the plurality of virtual function accelerators.
17 . The system of claim 15 , wherein the programmable logic device is configurable to:
determine that the third data is characterized as a first data type; and
in response to determining that the third data is characterized as the first data type, perform chained operations on the third data, wherein the chained operations comprise instructing a third virtual function accelerator to perform a third function on the third data to generate a fourth data.
18 . The system of claim 17 , wherein the first data type comprises an indication of a file type.
19 . The system of claim 17 , wherein the first data type comprises an indication of a priority level.
20 . The system of claim 15 , wherein the programmable logic device is configurable to:
determine that the third data is characterized as a second data type; and
in response to determining that the third data is characterized as the second data type, transmit the third data to the host processor.