Global coherence operations
A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.
1 . A device, comprising:
a cache memory that includes a set of lines;
a cache controller; and
a first cache pipeline coupled between the cache controller and the cache memory,
wherein the cache controller is configured to:
receive an operation directed to more than one line of the set of lines; and
based on the operation,
operate in a first mode to prevent any new one of a first type of non-blocking transaction from entering the first cache pipeline and permitting a new one of a second type of non-blocking transaction to enter the first cache pipeline;
determine whether the first cache pipeline contains any of the first type of non-blocking transaction;
based on the first cache pipeline being free of the first type of non-blocking transaction, transition from the first mode to a second mode to prevent any new one of the first type of non-blocking transaction and any new one of the second type of non-blocking transaction from entering the first cache pipeline;
determine whether the first cache pipeline contains any transaction; and based on the first cache pipeline being free of transactions, cause the first cache pipeline to perform the operation on the cache memory.
2 . The device of claim 1 , wherein the first type of non-blocking transaction includes a snoop transaction.
3 . The device of claim 1 , wherein the second type of non-blocking transaction includes a response transaction or a victim transaction.
4 . The device of claim 1 , wherein the cache controller is configured to:
based on the operation:
prior to the first mode, operate in a third mode to prevent any new one of a blocking transaction from entering the first cache pipeline;
determine whether first cache pipeline contains any blocking transaction; and
based on the first cache pipeline being free of blocking transactions, transition from the third mode to the first mode.
5 . The device of claim 4 , wherein the blocking transaction includes a read transaction, a write transaction, or an instruction fetch transaction.
6 . The device of claim 1 , wherein the operation includes an invalidate operation, a writeback invalidate operation, or a writeback operation.
7 . The device of claim 1 , wherein:
the cache memory includes a first bank and a second bank;
the first cache pipeline is associated with the first bank; and
the operation is associated with the first bank and the second bank.
8 . The device of claim 7 , wherein:
the device further comprises a second cache pipeline coupled between the cache controller and the second bank;
in the first mode, the first type of non-blocking transaction is not permitted to enter the second cache pipeline and the second type of non-blocking transaction is permitted to enter the second cache pipeline; and
in the second mode, the first type of non-blocking transaction and the second type of non-blocking transaction are not permitted to enter the second cache pipeline.
9 . The device of claim 1 , wherein the cache memory is a level-two (L2) cache memory and the cache controller is an L2 cache controller.
10 . The device of claim 1 , further comprising:
a set of cache pipelines that includes the first cache pipeline,
wherein the cache controller is configured to:
prior to causing the first cache pipeline to perform the operation on the cache memory, determine whether any pipeline of the set of pipelines, including the first cache pipeline, contains any transaction; and
based on the set of pipelines, including the first cache pipeline, being free of transactions, cause the first cache pipeline to perform the operation on the cache memory.
11 . A device comprising:
a cache memory that includes a set of lines;
a cache controller; and
a first cache pipeline coupled between the cache controller and the cache memory,
wherein the cache controller is configured to:
receive an operation directed to more than one line of the set of lines; and
based on the operation,
operate in a first mode to prevent any new one of a blocking transaction from entering the first cache pipeline and permit a new one of a non-blocking transaction to enter the first cache pipeline;
determine whether the first cache pipeline contains any blocking transaction; and
based on the first cache pipeline being free of the blocking transaction, transition from the first mode to a second mode to prevent any new one of the blocking transaction and any new one of a first type of the non-blocking transaction from entering the first cache pipeline and permit a new one of a second type of the non-blocking transaction to enter the first cache pipeline.
12 . The device of claim 11 , wherein the first type of non-blocking transaction includes a snoop transaction.
13 . The device of claim 11 , wherein the second type of non-blocking transaction includes a response transaction or a victim transaction.
14 . The device of claim 11 , wherein the blocking transaction includes a read transaction, a write transaction, or an instruction fetch transaction.
15 . The device of claim 11 , wherein the operation includes an invalidate operation, a writeback invalidate operation, or a writeback operation.
16 . The device of claim 11 , wherein the cache controller is configured to:
determine whether the first cache pipeline contains any of the first type of non-blocking transaction;
based on the first cache pipeline being free of the first type of non-blocking transaction, transition from the second mode to a third mode to prevent any new one of the first type of the non-blocking transaction and any new one of the second type of the non-blocking transaction from entering the first cache pipeline;
determine whether the first cache pipeline contains any transaction; and
based on the first cache pipeline being free of transactions, cause the first cache pipeline to perform the operation on the cache memory.
17 . The device of claim 16 , further comprising:
a set of cache pipelines that includes the first cache pipeline,
wherein the cache controller is configured to:
prior to causing the first cache pipeline to perform the operation on the cache memory,
determine whether any pipeline of the set of pipelines, including the first cache pipeline, contains any transaction; and
based on the set of pipelines, including the first cache pipeline, being free of transactions, cause the first cache pipeline to perform the operation on the cache memory.
18 . The device of claim 11 , wherein:
the cache memory includes a first bank and a second bank;
the first cache pipeline is associated with the first bank; and
the operation is associated with the first bank and the second bank.
19 . The device of claim 18 , wherein:
the device further comprises a second cache pipeline coupled between the cache controller and the second bank;
in the first mode, the blocking transaction is not permitted to enter the second cache pipeline and the non-blocking transaction is permitted to enter the second cache pipeline; and
in the second mode, the blocking transaction and the non-blocking transaction are not permitted to enter the second cache pipeline.
20 . The device of claim 11 , wherein the cache memory is a level-two (L2) cache memory and the cache controller is an L2 cache controller.