Parallel thread synchronization
Apparatuses, systems, and techniques to implement cooperative thread groups. In at least one embodiment, two or more groups of synchronized threads are synchronized and executed in parallel for efficient execution on a GPU.
1 . One or more processors, comprising: circuitry to distribute a processing task into two or more warps and cause each of the two or more warps to be performed concurrently in parallel using a separate multithreaded processor core, wherein a first group of the two or more warps is dependent on at least one warp in a second group of the two or more warps.
2 . The one or more processors of claim 1 , wherein the two or more warps are synchronized using a barrier stored in shared memory accessible to the two or more warps.
3 . The one or more processors of claim 2 , wherein:
the barrier is implemented as a counter; and
the barrier increments when each thread of the two or more warps are synchronized.
4 . The one or more processors of claim 2 , wherein:
the barrier is implemented as a counter; and
the barrier releases the two or more warps when the counter reaches a predetermined value.
5 . The one or more processors of claim 2 , wherein:
the barrier is implemented as a bit field; and
each bit of the bit field represents a different thread of the two or more warps.
6 . The one or more processors of claim 2 , wherein:
the barrier is implemented as a bit field; and
each bit of the bit field is modified when a corresponding thread of the two or more warps is synchronized.
7 . The one or more processors of claim 1 , wherein the two or more warps are part of a cooperative thread group.
8 . The one or more processors of claim 1 , wherein:
the two or more warps comprise threads that are part of a cooperative thread group; and
a number of threads in the cooperative thread group is restricted to a power of 2.
9 . The one or more processors of claim 1 , wherein each of the two or more warps comprise different groups of threads of a single cooperative thread group, wherein each group of threads is capable of being executed in parallel by a symmetric multiprocessor core.
10 . The one or more processors of claim 9 , wherein the circuitry causes each group of the different groups of threads to be executed in parallel.
11 . The one or more processors of claim 9 , wherein the different groups of threads is the same size.
12 . The one or more processors of claim 9 , wherein the different groups of threads are synchronized by a barrier.
13 . The one or more processors of claim 1 , wherein:
the circuitry synchronizes a plurality of cooperative groups; and
the plurality of cooperative groups are part of a cooperative thread array.
14 . The one or more processors of claim 13 , wherein the circuitry synchronizes the plurality of cooperative groups using a barrier.
15 . The one or more processors of claim 1 , wherein:
the two or more warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier; and
the barrier is implemented as a counter that increments when each of the different subgroups of threads is synchronized.
16 . The one or more processors of claim 1 , wherein:
the two or more warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier;
the barrier is implemented as a bit field; and
each bit of the bit field corresponds to each of the different subgroups of threads.
17 . A computer-implemented method comprising:
generating a cooperative thread group to perform a processing task, the cooperative thread group comprising two or more dependent warps;
performing a first warp of the two or more dependent warps of the cooperative thread group in a first multithreaded processor core in parallel with a second warp of the two or more dependent warps of the cooperative thread group in a second multithreaded processor core; and
releasing a memory corresponding to the cooperative thread group based, at least in part, on an identification that all of the two or more dependent warps are performed.
18 . The computer-implemented method of claim 17 , wherein the two or more dependent warps are synchronized using a barrier stored in shared memory accessible to the two or more dependent warps.
19 . The computer-implemented method of claim 18 , wherein:
the barrier is implemented as a counter; and
the barrier increments when each thread of the two or more dependent warps are synchronized.
20 . The computer-implemented method of claim 18 , wherein:
the barrier is implemented as a counter; and
the barrier releases the two or more dependent warps when the counter reaches a predetermined value.
21 . The computer-implemented method of claim 18 , wherein:
the barrier is implemented as a bit field; and
each bit of the bit field represents a different thread of the two or more dependent warps.
22 . The computer-implemented method of claim 18 , wherein:
the barrier is implemented as a bit field; and
each bit of the bit field is modified when a corresponding thread of the two or more dependent warps is synchronized.
23 . The computer-implemented method of claim 17 , wherein the two or more dependent warps are part of a cooperative thread group.
24 . The computer-implemented method of claim 17 , wherein:
the two or more dependent warps comprise threads that are part of a cooperative thread group; and
a number of threads in the cooperative thread group is restricted to a power of 2.
25 . The computer-implemented method of claim 17 , wherein each of the two or more dependent warps comprise different groups of threads of the cooperative thread group, wherein each group of threads is capable of being executed in parallel by a symmetric multiprocessor core.
26 . The computer-implemented method of claim 25 , further comprising causing each group of the different groups of threads to be executed in parallel.
27 . The computer-implemented method of claim 25 , wherein the different groups of threads is the same size.
28 . The computer-implemented method of claim 25 , wherein the different groups of threads are synchronized by a barrier.
29 . The computer-implemented method of claim 17 , further comprising synchronizing a plurality of cooperative groups, the plurality of cooperative groups are part of a cooperative thread array.
30 . The computer-implemented method of claim 29 , wherein synchronizing the plurality of cooperative groups comprises using a barrier.
31 . The computer-implemented method of claim 17 , wherein:
the two or more dependent warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier; and
the barrier is implemented as a counter that increments when each of the different subgroups of threads is synchronized.
32 . The computer-implemented method of claim 17 , wherein:
the two or more dependent warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier;
the barrier is implemented as a bit field; and
each bit of the bit field corresponds to each of the different subgroups of threads.
33 . A computer system, comprising:
one or more processors and memory storing executable instructions that, as a result of being executed by the one or more processors, distribute a processing task into two or more warps and cause each of the two or more warps to be performed concurrently in parallel using a separate multithreaded processor core, wherein a first group of the two or more warps is dependent on at least one warp in a second group of the two or more warps.
34 . The computer system of claim 33 , wherein the two or more warps are synchronized using a barrier stored in shared memory accessible to the two or more warps.
35 . The computer system of claim 34 , wherein:
the barrier is implemented as a counter; and
the barrier increments when each thread of the two or more warps are synchronized.
36 . The computer system of claim 34 , wherein:
the barrier is implemented as a counter; and
the barrier releases the two or more warps when the counter reaches a predetermined value.
37 . The computer system of claim 34 , wherein:
the barrier is implemented as a bit field; and
each bit of the bit field represents a different thread of the two or more warps.
38 . The computer system of claim 34 , wherein:
the barrier is implemented as a bit field; and
each bit of the bit field is modified when a corresponding thread of the two or more warps is synchronized.
39 . The computer system of claim 33 , wherein the two or more warps are part of a cooperative thread group.
40 . The computer system of claim 33 , wherein:
the two or more warps comprise threads that are part of a cooperative thread group; and
a number of threads in the cooperative thread group is restricted to a power of two.
41 . The computer system of claim 33 , wherein each of the two or more warps comprise different groups of threads of a single cooperative thread group, wherein each group of threads is capable of being executed in parallel by a symmetric multiprocessor core.
42 . The computer system of claim 41 , wherein the executable instructions further cause each group of the different groups of threads to be executed in parallel.
43 . The computer system of claim 41 , wherein the different groups of threads is the same size.
44 . The computer system of claim 41 , wherein the different groups of threads are synchronized by a barrier.
45 . The computer system of claim 33 , wherein:
the executable instructions further cause the computer system to synchronize a plurality of cooperative groups; and
the plurality of cooperative groups are part of a cooperative thread array.
46 . The computer system of claim 45 , wherein the computer system synchronizes the plurality of cooperative groups using a barrier.
47 . The computer system of claim 33 , wherein:
the two or more warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier; and
the barrier is implemented as a counter that increments when each of the different subgroups of threads is synchronized.
48 . The computer system of claim 33 , wherein:
the two or more warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier;
the barrier is implemented as a bit field; and
each bit of the bit field corresponds to each of the different subgroups of threads.
49 . A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, distribute a processing task into two or more warps and cause each of the two or more warps to be performed concurrently in parallel using a separate multithreaded processor core, wherein a first group of the two or more warps is dependent on at least one warp in a second group of the two or more warps.
50 . The machine-readable medium of claim 49 , wherein the two or more warps are synchronized using a barrier stored in shared memory accessible to the two or more warps.
51 . The machine-readable medium of claim 50 , wherein:
the barrier is implemented as a counter; and
the barrier increments when each thread of the two or more warps are synchronized.
52 . The machine-readable medium of claim 50 , wherein:
the barrier is implemented as a counter; and
the barrier releases the two or more warps when the counter reaches a predetermined value.
53 . The machine-readable medium of claim 50 , wherein:
the barrier is implemented as a bit field; and
each bit of the bit field represents a different thread of the two or more warps.
54 . The machine-readable medium of claim 49 , wherein the two or more warps are part of a cooperative thread group.
55 . The machine-readable medium of claim 49 , wherein:
the two or more warps comprise threads that are part of a cooperative thread group; and
a number of threads in the cooperative thread group is restricted to a power of two.
56 . The machine-readable medium of claim 49 , wherein each of the two or more warps comprise different groups of threads of a single cooperative thread group, wherein each group of threads is capable of being executed in parallel by a symmetric multiprocessor core.
57 . The machine-readable medium of claim 56 , wherein the instructions further cause each group of the different groups of threads to be executed in parallel.
58 . The machine-readable medium of claim 49 , wherein:
the instructions further cause the one or more processors to synchronize a plurality of cooperative groups; and
the plurality of cooperative groups are part of a cooperative thread array.
59 . The machine-readable medium of claim 49 , wherein:
the two or more warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier; and
the barrier is implemented as a counter that increments when each of the different subgroups of threads is synchronized.
60 . The machine-readable medium of claim 49 , wherein:
the two or more warps are each organized into different subgroups of threads;
the different subgroups of threads are synchronized using a barrier;
the barrier is implemented as a bit field; and
each bit of the bit field corresponds to each of the different subgroups of threads.