Proactive correction of potential transmission errors in a storage device
Instead of incurring interface errors caused by power drops, continuously track all the channels between the controller and the storage device (both in-band and side-band channels). The tracking will include extracting relevant indications and use a prediction model that correlates between the tracked indications to later occurrence of power drop events. In response to the prediction results, the system may perform different rehabilitation operations (countermeasures). The controller will monitor different indications from the storage element and power supply to predict a signal integrity degradation marginality event on the interface. The monitoring and mitigation strategy relies on an open-ended system. The controller does not employ a real-time continuous return channel from the storage device that may signal pass/fail conditions. Given the nature of an open-ended system and tolerance of calibration for the data gathering, processing and inference system, the controller will have to cope also with false positive events.
1 . A data storage device, comprising:
a memory device, wherein the memory device comprises NAND chips;
multiple interfaces coupled to the NAND chips, wherein the multiple interfaces have a plurality of channels; and
a controller coupled to the multiple interfaces, wherein the controller is configured to:
monitor signals of the plurality of channels to determine one or more indications of power stability of the data storage device, wherein the one or more indications of power stability indicates whether the multiple interfaces will suffer a reduced signal integrity, wherein the controller will monitor each channel, wherein the monitoring comprises:
tracking a state of a power supply of the data storage device;
tracking a power drop ratio of peak power to average power; and
tracking a read data correctable error count;
predict, using a prediction model correlating the one or more indications of power stability to later occurrences of power drop events, that the interface will suffer reduced signal integrity; and
initiate corrective action to mitigate effects of the reduced signal integrity based on results from the prediction model, wherein the corrective action is reducing parallelism by operating with less channels at a time.
2 . The data storage device of claim 1 , wherein monitoring the plurality of channels further comprises tracking data electrical parameter signals at input/output (I/O) pins; control electrical parameter signals at I/O pins; and amount of simultaneous switching outputs (SSO); crosstalk of data transmitted; controller silicon temperature; memory device temperature; and controller silicon process corner variation.
3 . The data storage device of claim 1 , wherein predicting that the interface will suffer reduced signal integrity is performed statically.
4 . The data storage device of claim 3 , wherein predicting that the interface will suffer reduced signal integrity performed statically is based upon tuning performed offline.
5 . The data storage device of claim 1 , wherein predicting that the interface will suffer reduced signal integrity is performed dynamically and is based upon:
tuning performed offline; and
tuning parameters updated dynamically along a lifetime of the device, wherein the tuning parameters updated dynamically along the lifetime of the device comprise aging parameters for NAND, controller silicon, and passive components.
6 . The data storage device of claim 1 , wherein predicting that the interface will suffer reduced signal integrity comprises utilizing a risk level, wherein the risk level is a probability measurement of whether a prediction is correct.
7 . The data storage device of claim 1 , wherein monitoring the plurality of channels occurs in a monitoring module in the memory device.
8 . The data storage device of claim 1 , wherein monitoring the plurality of channels occurs in a monitoring module in the controller.
9 . The data storage device of claim 1 , wherein the controller is configured to write data to the memory device and wherein predicting that the interface will suffer reduced signal integrity comprises predicting whether the data written to the memory device needs to be resubmitted.
10 . The data storage device of claim 9 , wherein the controller is configured to write the data to volatile memory upon determining that the data needs to be resubmitted.
11 . The data storage device of claim 1 , wherein the controller comprises a predictor module configured to receive information on the plurality of channels being monitored.
12 . The data storage device of claim 1 , wherein tracking the read data correctable error count comprises reading data from a net data and control electrical parameter signals measured physically at one or more input/output (I/O) pins of the data storage device.
13 . A data storage device, comprising:
a memory device, wherein the memory device comprises NAND chips;
multiple interfaces coupled to the NAND chips, wherein the multiple interfaces have channels; and
a controller coupled to the multiple interfaces, wherein the controller includes a central processing unit (CPU) and the controller is configured to:
monitor signals from the channels between the controller and the memory device to determine one or more indications of power stability of the data storage device, wherein the one or more indications of power stability indicates whether the interfaces will suffer a reduced signal integrity, wherein the monitoring is for each channel and comprises:
tracking a state of a power supply of the data storage device;
tracking a power drop ratio of peak power to average power; and
tracking a read data correctable error count;
write data to the memory device;
predict, using a prediction model correlating the one or more indications of power stability to later occurrences of power drop events, a probability that the controller will suffer the reduced signal integrity;
write the data to volatile memory; and
initiate corrective action to mitigate effects of the reduced signal integrity based on results from the prediction model, wherein the corrective action is reducing parallelism by operating with less channels at a time.
14 . The data storage device of claim 13 , wherein the controller is configured to correlate the monitored signals to later occurrence of power drop events.
15 . The data storage device of claim 13 , wherein the monitoring further comprises monitoring temperature of the memory device.
16 . The data storage device of claim 13 , wherein the monitoring further comprises monitoring a number of computation intensive applications performed by the CPU.
17 . A data storage device, comprising:
means to store data, wherein the means to store data comprises NAND chips; and
a controller coupled to the multiple interfaces, wherein the controller comprises a prediction module and a flash interface module (FIM) that comprises one or multiple physical channels, wherein the FIM comprises multiple interfaces coupled to the NAND chips, wherein the controller is configured to:
monitor signals from the one or more multiple physical channels to determine one or more indications of power stability of the data storage device, wherein the one or more indications of power stability indicate whether the interface will suffer a reduced signal integrity, wherein the monitoring comprises:
tracking a state of a power supply of the data storage device;
tracking a power drop ratio of peak power to average power; and
tracking a read data correctable error count;
predict, using a prediction model correlating the one or more indications of power stability to later occurrences of power drop events, the reduced signal integrity at the interface between the controller and the means to store data; and
take corrective action in response to the predicting, wherein the corrective action improves the signal integrity of the interface between the controller and the means to store data, wherein the corrective action is reducing reducing parallelism by operating with less channels at a time.
18 . The data storage device of claim 17 , wherein the prediction module is coupled to a monitor that monitors channels between the FIM and the means to store data.
19 . The data storage device of claim 18 , wherein the monitor is disposed in the FIM.