Dynamic random access memory (DRAM) device with write error protection
Technologies for providing write protection to an integrated circuit memory device are described. The integrated circuit memory device has an input port to receive write data and command data and a read data output port to send read data. A device includes a write protection mechanism to prevent write data from being written to a memory core. The write protection mechanism can mask the write data or abort a write operation in response to activation. The write protection mechanism can be activated in response to an error detected by a serial data buffer (SDB) device coupled to the integrated circuit memory device.
1 . A dynamic random-access memory (DRAM) device comprising:
an input port to receive interleaved input comprising commands and write data;
a read data output port to output read data;
a memory core to store data including the write data and the read data; and
a write protection mechanism to selectively prevent the write data from being written to the memory core in response to receiving both an activated data select signal and an activated chip select signal.
2 . The DRAM device of claim 1 , wherein the write protection mechanism comprises an abort function.
3 . The DRAM device of claim 1 , wherein the write protection mechanism comprises a mask function.
4 . The DRAM device of claim 1 , wherein the write protection mechanism comprises an abort function and a mask function.
5 . The DRAM device of claim 1 , wherein the write protection mechanism is activated in response to an error detected by a serial buffer device coupled to the DRAM device over a serial link.
6 . The DRAM device of claim 1 , wherein the write protection mechanism is activated in response to at least one of a data error, an anomaly condition, an illegal command, or a timing error detected by a serial buffer device coupled to the DRAM device over a serial link.
7 . The DRAM device of claim 1 , further comprising a buffer to buffer the write data before a write operation of the write data, wherein the write protection mechanism is to prevent the write data from being written to the memory core from the buffer in response to the write operation.
8 . The DRAM device of claim 1 , wherein the write protection mechanism is to prevent the write data from being written to the memory core in response to an unused status state of a data select signal and a chip select signal, wherein the unused status state represents a write protection selection.
9 . A dynamic random-access memory (DRAM) device comprising:
an input port to receive at least one of commands or write data;
a read data output port to output read data;
a memory core to store data including the write data and the read data; and
a write protection mechanism to selectively prevent the write data from being written to the memory core in response to receiving both an activated data select signal and an activated chip select signal.
10 . A method of operating a dynamic random-access memory (DRAM) device having an input port to receive commands, and a read data output port, the method comprising:
receiving, at the input port of the DRAM device, write data to be written to a memory core of the DRAM device; and
selectively preventing, by a write protection mechanism of the DRAM device, the write data from being written to the memory core in response to receiving both an activated data select signal and an activated chip select signal.
11 . The method of claim 10 , wherein preventing the write data from being written comprises masking the write data.
12 . The method of claim 10 , wherein preventing the write data from being written comprises aborting a write operation associated with the write data.
13 . The method of claim 10 , further comprising buffering the write data before a write operation of the write data, wherein preventing the write data from being written comprises preventing the write data from being written to the memory core from the buffer in connection with the write operation.
14 . The method of claim 10 , wherein preventing the write data from being written comprises preventing the write data from being written to the memory core in response to an unused status state of a data select signal and a chip select signal, wherein the unused status state represents a write protection selection.
15 . The method of claim 10 , wherein preventing the write data from being written comprises preventing the write data from being written to the memory core in response to an error detected by a serial buffer device coupled to the DRAM device over a serial link.
16 . The method of claim 10 , wherein preventing the write data from being written comprises preventing the write data from being written to the memory core in response to at least one of a data error, an anomaly condition, an illegal command, or a timing error detected by a serial buffer device coupled to the DRAM device over a serial link.
17 . An integrated circuit memory device having a memory array, the integrated circuit memory device comprising:
a first port to receive interleaved input comprising commands and write data;
a second port to transmit read data retrieved from the memory array in response to a read command; and
a write protection circuit to selectively prevent the write data from being written to a group of cells in response to receiving both an activated data select signal and an activated chip select signal.
18 . The integrated circuit memory device of claim 17 , wherein the write protection circuit comprises at least one of a mask function or an abort function.
19 . An integrated circuit memory device having a memory array, the integrated circuit memory device comprising:
a first port to receive commands or write data;
a second port to transmit read data retrieved from the memory array in response to a read command; and
a write protection circuit to selectively prevent the write data from being written to a group of cells in response to both the data select signal and the chip select signal being both activated.