Post-mortem crash analysis for accelerated processors
A computing device and a method of performing crash analysis is provided. Each compute unit of an accelerated processor is configured to execute an application in a crash analysis operation mode, different from a normal operation mode, by executing a single instruction in isolation from any other instruction such that execution of the single instruction is completed prior to beginning execution of any of the other instructions. Examples of selectable crash analysis operation modes include a first mode in which execution of each memory instruction is completed prior to beginning execution of a next instruction, a second mode in which execution of each ALU instruction is completed prior to beginning execution of a next instruction, and a third mode in which execution of both memory and ALU instructions are completed prior to beginning execution of a next instruction.
1 . A computing device for performing crash analysis, the computing device comprising:
a memory storing application instructions; and
an accelerated processor, in communication with the memory, the accelerated processor comprising a plurality of compute units, each compute unit configured to execute the application instructions in a regular mode for regular parallel execution of the application instructions; and in a crash-analysis operation mode entered before the application instructions are dispatched,
wherein when in the crash-analysis operation mode, each of the plurality of compute units:
executes a single instruction in isolation such that execution of the single instruction is completed before a next instruction is issued; and
upon an error occurring during execution of any instruction, halts further issuance of instructions and notifies a central processing unit (CPU) that the error has occurred; and
wherein while a given compute unit executes the single instruction, the accelerated processor inhibits issuance of any instruction by the other compute units of the plurality of compute units until execution of the single instruction by the given compute unit is completed.
2 . The computing device of claim 1 , wherein executing the single instruction in isolation comprises:
completing execution of each memory instruction prior to beginning execution of a next instruction.
3 . The computing device of claim 1 , wherein executing the single instruction in isolation comprises:
completing execution of each arithmetic logic unit (ALU) instruction prior to beginning execution of a next instruction.
4 . The computing device of claim 1 , wherein executing the single instruction in isolation comprises:
completing execution of each memory instruction prior to beginning execution of a next instruction and completing execution of each ALU instruction prior to beginning execution of the next instruction.
5 . The computing device of claim 1 , wherein the computing device is further configured to select one of the regular mode and the crash-analysis operation mode to execute the application instructions.
6 . The computing device of claim 1 , wherein each compute unit is configured to halt execution of the application instructions on a condition that an error occurs during execution of the application instructions.
7 . The computing device of claim 1 , wherein the accelerated processor is further configured to generate and store crash analysis information over time during execution of the application instructions in the crash-analysis operation mode.
8 . The computing device of claim 7 , wherein the crash analysis information comprises at least one of:
one or more instructions executed;
a state of registers local to a compute unit; or
a state of memory local to the compute unit.
9 . The computing device of claim 1 , wherein in the crash-analysis operation mode each of the plurality of compute units further:
waits until all dependency counters indicate that the single instruction has fully completed before the next instruction is issued.
10 . A method for performing crash analysis for an application, comprising:
prior to dispatching the application, setting a graphics processing unit (GPU) that includes a plurality of compute units to a crash-analysis operation mode;
executing, by a plurality of compute units of the GPU, application instructions in the crash-analysis operation mode by:
executing a single instruction on each respective compute unit in isolation such that execution of the single instruction is completed before a next instruction is issued;
while a given compute unit executes the single instruction, inhibiting issuance of any instruction by the other compute units of the plurality of compute units until execution of the single instruction by the given compute unit is completed, and
halting execution of the application upon detection of any error and notifying a central processing unit that the error has occurred.
11 . The method of claim 10 , wherein executing the single instruction in isolation comprises:
completing execution of each memory instruction prior to beginning execution of the next instruction.
12 . The method of claim 10 , wherein executing the single instruction in isolation comprises completing execution of each arithmetic-logic-unit (ALU) instruction prior to beginning execution of the next instruction.
13 . The method of claim 10 , wherein executing the single instruction in isolation comprises:
completing execution of each memory instruction prior to beginning execution of the next instruction and completing execution of each ALU instruction prior to beginning execution of the next instruction.
14 . The method of claim 10 , further comprising selecting one of the regular mode and the crash-analysis operation mode to execute the application.
15 . The method of claim 10 , wherein halting execution further comprises stopping issuance of further instructions by the plurality of compute units.
16 . The method of claim 10 , further comprising generating and storing crash analysis information over time during execution of the application in the crash-analysis operation mode.
17 . The method of claim 16 , wherein the crash analysis information comprises at least one of:
one or more instructions executed;
a state of registers local to a compute unit; or
a state of memory local to the compute unit.
18 . The method of claim 16 , further comprising at least one of
displaying the crash analysis information on a display device or
sending the crash analysis information to one or more remote devices over a network.
19 . A device for performing crash analysis for an application, the device comprising:
a first processor configured to execute at least a first portion of the application;
a memory storing application instructions for a second portion of the application; and
a second processor in communication with the memory, comprising a plurality of compute units, each compute unit configured to execute the application instructions stored in the memory in a regular mode for regular parallel execution of the application instructions; and in a crash-analysis operation mode entered before the application is dispatched,
wherein when in the crash-analysis operation mode, each of the plurality of compute units:
executes a single instruction in isolation such that execution of that single instruction is completed before a next instruction is issued; and
upon an error occurring during execution of any instruction, halts further issuance of instructions and notifies the first processor that the error has occurred,
wherein while a given compute unit executes the single instruction, the device inhibits issuance of any instruction by the other compute units of the plurality of compute units until execution of the single instruction by the given compute unit is completed.
20 . The device of claim 19 , wherein executing the application instructions in isolation from each other comprises:
completing execution of each memory instruction prior to beginning execution of a next instruction.