Method and apparatus for applying ECC to memory in artificial neural network based system semiconductor
A method for applying error correction code (ECC) to a memory performed by an apparatus for applying ECC to a memory in an artificial neural network-based system semiconductor, includes dividing memory cells into a plurality of groups of memory cell arrays corresponding to first to n-th frames based on word lines, wherein n is a natural number greater than or equal to 2, performing an ECC write or read operation by applying ECC to a memory cell array of a group corresponding to each of the first to n-th frames, and performing a general write or read operation without applying ECC to the memory cell array of the remaining groups excluding the group corresponding to each of the first to n-th frames.
1 . A method for applying an error correction code (ECC) to a memory in an artificial neural network-based system semiconductor, the method comprising:
dividing memory cells into a plurality of groups of memory cell arrays corresponding to first to n-th frames based on word lines, wherein n is a natural number greater than or equal to 2;
performing an ECC write or read operation by applying the ECC to a memory cell array of a group corresponding to each of the first to n-th frames; and
performing a general write or read operation without applying the ECC to the memory cell array of the remaining groups excluding the group corresponding to each of the first to n-th frames,
wherein a number of the ECC write or read operation by applying the ECC and the general write or read operation is adjusted according to fault handing time interval (FTTI) time and a frame processing time.
2 . The method of claim 1 , wherein, in the ECC write operation, the ECC is generated by an ECC encoder based on write data in the memory cell array of the group corresponding to each frame selected by an address decoder based on the word lines, and the write data is stored in the memory and the generated ECC is stored in an ECC memory.
3 . The method of claim 1 , wherein, in the ECC read operation, the ECC is regenerated from the memory cell array of the group corresponding to each frame selected by an address decoder based on the word lines, and the regenerated ECC is compared with the ECC read from an ECC memory.
4 . The method of claim 1 , wherein, in the performing of the ECC write or read operation, the ECC is applied to the memory cell array of the group corresponding to each frame selected based on a least significant bit (LSB) of address decoder input information.
5 . The method of claim 1 , wherein, in the performing of the general write or read operation, a write or read operation is performed by adding a parity bit for error detection to the memory cell array of the remaining groups excluding the group corresponding to each of the first to n-th frames.
6 . The method of claim 1 , wherein, in the performing of the general write or read operation, an error is detected by calculating the number of bits by combining read data and a parity bit of a selected word line based on an LSB of address decoder input information in the memory cell array of the remaining groups excluding the group corresponding to each frame.
7 . An apparatus for applying an error correction code (ECC) to a memory in an artificial neural network-based system semiconductor, the apparatus comprising:
a memory cell configured to store data generated by the artificial neural network-based system semiconductor;
an ECC memory configured to store the ECC related to an ECC write or read operation;
a storage module configured to store one or more programs; and
a processor configured to execute the one or more stored programs,
wherein the processor is configured to:
divide memory cells into a plurality of groups of memory cell arrays corresponding to first to n-th frames based on word lines, wherein n is a natural number greater than or equal to 2,
perform the ECC write or read operation by applying the ECC to a memory cell array of a group corresponding to each of the first to n-th frames, and
perform a general write or read operation without applying the ECC to the memory cell array of the remaining groups excluding the group corresponding to each of the first to n-th frames,
wherein a number of ECC applications applicable to the ECC write or read operation and the general write or read operation is adjusted according to fault handing time interval (FTTI) time and frame processing time.
8 . The apparatus of claim 7 , wherein, in the ECC write operation, the ECC is generated by an ECC encoder based on write data in the memory cell array of the group corresponding to each frame selected by an address decoder based on the word lines, and the write data is stored in the memory and the generated ECC is stored in the ECC memory.
9 . The apparatus of claim 7 , wherein, in the ECC read operation, the ECC is regenerated from the memory cell array of the group corresponding to each frame selected by an address decoder based on the word lines, and the regenerated ECC is compared with the ECC read from the ECC memory.
10 . The apparatus of claim 7 , wherein the processor is configured to apply the ECC to the memory cell array of the group corresponding to each frame selected based on a least significant bit (LSB) of address decoder input information.
11 . The apparatus of claim 7 , wherein the processor performs a write or read operation by adding a parity bit for error detection to the memory cell array of the remaining groups excluding the group corresponding to each of the first to n-th frames.
12 . The apparatus of claim 7 , wherein the processor is configured to detect an error by calculating the number of bits by combining read data and a parity bit of a selected word line based on an LSB of address decoder input information in the memory cell array of the remaining groups excluding the group corresponding to each frame.