Syndrome calculation
A syndrome can be calculated by storing data in a first array of memory cells and calculating syndromes utilizing the data, a first circuitry, and the first array of memory cells. The syndromes can be copied to a second array of memory cells. A decoding operation can be performed utilizing the plurality of syndromes, the second array of memory cells, and a second circuitry, where the first circuitry and the second circuitry are independent from each other.
1 . A method, comprising:
performing, by a second circuitry, a first decoding operation utilizing a second plurality of syndromes and a plurality of decision engines;
calculating a first plurality of syndromes utilizing a data, a first circuitry, and a first array of memory cells wherein the first circuitry does not include a decision engine;
providing the first plurality of syndromes to a second array of memory cells;
receiving, by the second circuitry, the first plurality of syndromes from the second array of memory cells; and
performing a second decoding operation utilizing the first plurality of syndromes, the second array of memory cells, the second circuitry, and the plurality of decision engines,
wherein the first circuitry and the second circuitry are independent from each other, and
wherein the second circuitry includes the plurality of decision engines configured to correct bit-flip errors in the first plurality of syndromes.
2 . The method of claim 1 , wherein the first plurality of syndromes are calculated utilizing a codeword, the first circuitry, and the first array of memory cells, wherein the data is the codeword.
3 . The method of claim 1 , wherein the first circuitry comprises fewer processing channels than the second circuitry.
4 . The method of claim 3 , wherein the first circuitry comprises fewer shift circuitry than the second circuitry.
5 . The method of claim 3 , wherein the first circuitry comprises fewer multiplexor (MUX) gates and de-MUX gates than the second circuitry.
6 . The method of claim 1 , further comprising providing the first plurality of syndromes from the first array of memory cells to the second array of memory cells in parallel.
7 . The method of claim 1 , further comprising providing the first plurality of syndromes from the first array of memory cells to the second array of memory cells sequentially.
8 . An apparatus comprising:
a first array of memory cells configured to store a first plurality of syndromes;
first circuitry coupled to the first array of memory cells and configured to calculate the first plurality of syndromes utilizing the first codeword and the first array of memory cells concurrently with a performance of a first decoding operation, wherein the first circuitry does not include a decision engine; and
a second array of memory cells configured to:
receive the first plurality of syndromes from the first array of memory cells; and
second circuitry coupled to the second array of memory cells and configured to:
perform the first decoding operation utilizing a second plurality of syndromes, and a plurality of decision engines, wherein the plurality of decision engines are configured to correct bit-flip errors;
receive the first plurality of syndromes from the second array of memory cells; and
perform a second decoding operation utilizing the first plurality of syndromes, the second array of memory cells, and the plurality of decision engines.
9 . The apparatus of claim 8 , wherein the first circuitry is further configured to calculate the first plurality of syndromes concurrently with a performance of an iteration of the first decoding operation.
10 . The apparatus of claim 8 , wherein the first circuitry is further configured to calculate the first plurality of syndromes concurrently with a performance of a plurality of iterations of the first decoding operation.
11 . The apparatus of claim 8 , wherein the first circuitry has a same quantity of channels as the second circuitry.
12 . The apparatus of claim 8 , wherein the first circuitry has a different quantity of channels as the second circuitry.
13 . The apparatus of claim 8 , wherein a first quantity of memory cells in the first array is equal to a second quantity of memory cells in the second array.
14 . The apparatus of claim 8 , wherein:
the first array of memory cells is further configured to receive a first codeword prior to storing the first codeword in a first memory device; and
the first circuitry is further configured to calculate the first plurality of syndromes utilizing the first codeword concurrently with the performance of the first decoding operation.
15 . The apparatus of claim 14 , wherein:
the first array of memory cells is further configured to receive a second codeword prior to storing the second codeword in a second memory device; and
the first circuitry is further configured to calculate a third plurality of syndromes utilizing the second codeword concurrently with the performance of the second decoding operation.
16 . An apparatus comprising:
a first array of memory cells configured to:
receive a first codeword prior to storing the first codeword in a memory device;
store a plurality of syndromes;
first circuitry coupled to the first array of memory cells and configured to calculate the plurality of syndromes utilizing the first codeword and the first array of memory cells concurrently with a performance of a first decoding operation and wherein the first circuitry does not include a decision engine;
second circuitry coupled to the first array of memory cells and configured to:
receive the plurality of syndromes from the first array of memory cells;
perform a second decoding operation utilizing the plurality of syndromes received from the first array and a plurality of decision engines configured to correct bit-flip errors.
17 . The apparatus of claim 16 , wherein the second circuitry is further configured to:
determine whether a quantity of errors for at least one syndrome of the plurality of syndromes is greater than a threshold quantity of errors;
responsive to determining that the quantity of errors is greater than the threshold quantity of errors, provide the plurality of syndromes to a decoding circuitry; and
responsive to determining that the quantity of errors is equal to zero, mark the codeword as being decoded.
18 . The apparatus of claim 17 , wherein the second circuitry is further configured to responsive to determining that the quantity of errors is greater than the threshold quantity of errors, provide the plurality of syndromes to the decoding circuitry comprising a second array of memory cells.
19 . The apparatus of claim 16 , wherein the second circuitry is further coupled to a second array of memory cells and is further configured to perform the first decoding operation utilizing different syndromes received from the second array of memory cells.