Discard control metadata
Interconnect circuitry comprises: receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent. The discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.
1 . Interconnect circuitry comprising:
receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and
transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent;
the discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.
2 . The interconnect circuitry according to claim 1 , comprising control circuitry configured to cache the discard-eligibility metadata received from the metadata-transmitting caching agent for the given cache line in a shared system cache shared between a plurality of caching agents.
3 . The interconnect circuitry according to claim 2 , in which the control circuitry is configured to discard the discard-eligibility metadata for the given cache line from the shared system cache upon eviction of the given cache line from the shared system cache.
4 . The interconnect circuitry according to claim 2 , in which the transmitting interface circuitry is configured to transmit the discard control metadata cached in the shared system cache for the given cache line to the metadata-receiving caching agent in response to a linefill request received from the metadata-receiving caching agent requesting that the given cache line is allocated into the private cache of the metadata-receiving caching agent.
5 . The interconnect circuitry according to claim 1 , in which the transmitting interface circuitry is configured to support transmission of the discard control metadata set by the metadata-transmitting caching agent to the metadata-receiving caching agent, in a case where the metadata-receiving caching agent is a different caching agent to the metadata-transmitting caching agent.
6 . The interconnect circuitry according to claim 1 , in which the receiving interface circuitry is configured to receive the discard control metadata from the metadata-transmitting caching agent in a snoop data response which responds to a snoop request previously transmitted to the metadata-transmitting caching agent.
7 . The interconnect circuitry according to claim 6 , in which the metadata-receiving caching agent is a different caching agent to the metadata-transmitting caching agent; and
the transmitting interface circuitry is configured to transmit to the metadata-receiving caching agent a snoop forward response specifying the discard control metadata obtained from the snoop data response.
8 . The interconnect circuitry according to claim 1 , in which the receiving interface circuitry is configured to receive from the metadata-transmitting caching agent a writeback message or eviction message specifying the discard control metadata for the given cache line.
9 . The interconnect circuitry according to claim 1 , in which the transmitting interface circuitry is configured to transmit to the metadata-receiving caching agent a read data message providing read data and the discard control metadata for the given cache line to be allocated into the private cache of the metadata-receiving caching agent.
10 . The interconnect circuitry according to claim 1 , in which the discard control metadata comprises discard-indicating metadata indicating whether the given cache line is a discardable cache line.
11 . The interconnect circuitry according to claim 1 , in which the discard control metadata comprises discard-eligibility metadata indicating whether the given cache line is eligible to become a discardable cache line upon occurrence of a mark-dead event.
12 . The interconnect circuitry according to claim 1 , comprising control circuitry responsive to a mark-dead event request received from a given caching agent to cause a target cache line identified by the mark-dead event request to be treated as a discardable cache line.
13 . The interconnect circuitry according to claim 12 , in which, in response to the mark-dead event request, whether the target cache line becomes treated as the discardable cache line is dependent on whether the discard control metadata associated with the target cache line indicates that the target cache line is eligible to become a discardable cache.
14 . The interconnect circuitry according to claim 12 , in which the control circuitry is configured to cause the target cache line to become treated as a discardable cache line in a system cache shared between a plurality of caching agents.
15 . The interconnect circuitry according to claim 12 , in which the control circuitry is configured to forward the mark-dead event request to a further caching agent, to cause the target cache line to become treated as a discardable cache line at the private cache of the further caching agent.
16 . The interconnect circuitry according to claim 1 , comprising home node circuitry configured to manage coherency of data cached in private caches of a plurality of caching agents.
17 . A system comprising:
the interconnect circuitry of claim 1 , implemented in at least one packaged chip;
at least one system component; and
a board,
wherein the at least one packaged chip and the at least one system component are assembled on the board.
18 . A chip-containing product comprising the system of claim 17 , wherein the system is assembled on a further board with at least one other product component.
19 . Non-transitory computer-readable storage medium to store code for fabrication of interconnect circuitry comprising:
receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and
transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent;
the discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.
20 . A method comprising:
receiving, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and
transmitting the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent;
the discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.