Packet processing device to determine memory to store data in a server architecture and computing system including same

1 . An apparatus of a packet processing device, the apparatus comprising:

a network interface to receive data packets from a network, and a host interface to connect to a server architecture, the server architecture having a plurality of computing units and a plurality of memory circuitries coupled to the computing units, the plurality of memory circuitries including a plurality of caches that correspond to a respective plurality of physical cache locations; and

a packet processing circuitry coupled to the network interface and to the host interface, the packet processing circuitry to:

determine a computing unit of the server architecture, the computing unit to execute a workload;

receive, through the network interface, a data packet including data to be used by the computing unit to execute the workload;

select, from the plurality of memory circuitries, a memory circuitry having a physical cache location with a shortest access distance to a physical location of the computing unit to execute the workload; and

route the data to the server architecture through the host interface for storage at the memory circuitry for access by the computing unit to execute the workload.

2 . The apparatus of claim 1 , wherein the packet processing circuitry is to select the memory circuitry of the server architecture by determining the plurality of physical cache locations.

3 . The apparatus of claim 2 , wherein the packet processing circuitry is to determine the plurality of physical cache locations based on an access distance between the physical cache locations and the physical location of the computing unit to execute the workload.

4 . The apparatus of claim 1 , wherein the packet processing circuitry is to select the memory circuitry by determining an association between at least one of the workload or the data with at least one of the computing unit or the memory circuitry.

5 . The apparatus of claim 2 , wherein the packet processing circuitry is to determine the plurality of physical cache locations to be one or more available physical cache locations physically closest to the physical location of the computing unit to execute the workload.

6 . The apparatus of claim 2 , wherein the packet processing circuitry is to determine the plurality of physical cache locations based on a state of the server architecture including at least one of: an amount of storage space available at one or more of the plurality of memory circuitries, a consumption rate of data from the plurality of memory circuitries, an amount of storage space available at the plurality of memory circuitries, a consumption rate of data from the plurality of memory circuitries, a processing speed of one or more of the computing units, or remaining processing times for workloads being or in a queue to be processed by one or more of the computing units.

7 . The apparatus of claim 6 , wherein the packet processing circuitry is to determine the physical cache locations based on historical information on a state of the server architecture.

8 . The apparatus of claim 6 , wherein the packet processing circuitry is to select the one or more physical cache locations of the memory circuitry based on information sent to it regarding a current state of the server architecture.

9 . A non-transitory computer-readable storage medium comprising instructions stored thereon, that when executed by one or more processors of a packet processing device, cause the one or more processors to:

determine a computing unit of a server architecture, the computing unit to execute a workload;

receive, through a network interface of the packet processing device, a data packet including data to be used by the computing unit to execute the workload;

select, from a plurality of memory circuitries of the server architecture, a memory circuitry having a physical cache location with a shortest access distance to a physical location of the computing unit to execute the workload; and

route the data to the server architecture through a host interface of the packet processing device for storage at the memory circuitry for access by the computing unit to execute the workload.

10 . The storage medium of claim 9 , the instructions to cause the one or more processors to select the memory circuitry of the server architecture by determining a plurality of physical cache locations corresponding to respective ones of the plurality of memory circuitries.

11 . The storage medium of claim 10 , the instructions to cause the one or more processors to determine the plurality of physical cache locations based on an access distance between the plurality of physical cache locations and the physical location of the computing unit to execute the workload.

12 . The storage medium of claim 9 , the instructions to cause the one or more processors to select the memory circuitry by determining an association between at least one of the workload or the data with at least one of the computing unit or the memory circuitry.

13 . The storage medium of claim 9 , the instructions to cause the one or more processors to select the memory circuitry based on load balancing for workloads as between computing units of the server architecture.

14 . The storage medium of claim 9 , the instructions to cause the one or more processors to select the memory circuitry based on a coordinated scheduling of data routing operations of the packet processing device with workload processing operations of one or more computing units of the server architecture.

15 . A method to be performed at a packet processing circuitry of a packet processing device, the method including:

determining a computing unit of a server architecture, the computing unit to execute a workload;

receiving, through a network interface of the packet processing device, a data packet including data to be used by the computing unit to execute the workload;

selecting, from a plurality of memory circuitries of the server architecture, a memory circuitry having a physical cache location with a shortest access distance to a physical location of the computing unit to execute the workload; and

routing the data to the server architecture through a host interface of the packet processing device for storage at the memory circuitry for access by the computing unit to execute the workload.

16 . The method of claim 15 , further including selecting the memory circuitry of the server architecture by determining a plurality of physical cache locations corresponding to respective ones of the plurality of memory circuitries.

17 . The method of claim 16 , wherein the workload is a first workload corresponding to a first portion of a program, the computing unit to execute the first workload is a first computing unit to execute the first workload, the data packet is a first data packet, and the data of the data packet is first data of the data packet, the memory circuitry is a first memory circuitry, and the physical cache location is a first physical cache location, further including:

determining a second computing unit of the server architecture to execute a second workload, the second workload corresponding to a second portion of the program;

receiving, through the network interface of the packet processing device, a second data packet including second data to be used by the second computing unit to execute the second workload;

selecting, from the plurality of memory circuitries of the server architecture, a second memory circuitry having a second physical cache location with a shortest access distance to a physical location of the second computing unit to execute the second workload; and

routing the second data to the server architecture through the host interface of the packet processing device for storage at the second memory circuitry for access by the second computing unit to execute the second workload.

18 . The method of claim 17 , further including determining the first data and the second data based on respective types thereof.

19 . A computing system of a data center, the computing system including:

a server architecture including a plurality of computing units and a plurality of memory circuitries coupled to the computing units, the plurality of memory circuitries including a plurality of caches that correspond to a respective plurality of physical cache locations; and

a packet processing device comprising:

a network interface to receive data packets from a network, and a host interface to connect to the server architecture; and

a packet processing circuitry coupled to the network interface and to the host interface, the packet processing circuitry to:

determine a computing unit of the server architecture, the computing unit to execute a workload;

receive, through the network interface, a data packet including data to be used by the computing unit to execute the workload;

select, from the plurality of memory circuitries, a memory circuitry having a physical cache location with a shortest access distance to a physical location of the computing unit to execute the workload; and

route the data to the server architecture through the host interface for storage at the memory circuitry for access by the computing unit to execute the workload.

20 . The computing system of claim 19 , wherein the packet processing circuitry is to select the memory circuitry of the server architecture by determining the plurality of physical cache locations.