Method and apparatus to perform packet switching between services on different processors in a compute node in a server
A processor-to-processor agent to provide connectivity over a processor-to-processor interconnect between services/network functions on different processors on a same compute node in a server is provided. The processor-to-processor agent can intercept socket interface calls using a network traffic filter in the network stack and redirect the packets based on traffic matching rules.
1 . A compute node comprising:
an interface to a network; and
two or more processors, a processor comprising:
a processor interconnect; and
circuitry to redirect, via a programmable processor-to-processor agent of the processor, a first packet received from an application to be transmitted to another application in another processor, the circuitry to redirect the first packet via the processor interconnect to the other application in the other processor based on an action associated with a destination address in the first packet;
wherein:
the programmable processor-to-processor agent is to exchange rule data with another programmable processor-to-processor agent of the other processor; and
the programmable processor-to-processor agent and the another programmable processor-to-processor agent are to implement packet redirection via the processor interconnect based, at least in part, upon the rule data.
2 . The compute node of claim 1 , wherein the circuitry to redirect a second packet received from the application via the interface to the network to the other application in the other processor.
3 . The compute node of claim 1 , wherein the action is to forward the first packet to the other application in the other processor.
4 . The compute node of claim 1 , wherein the processor interconnect is a Point-to-Point processor interconnect.
5 . The compute node of claim 4 , wherein the Point-to-Point Processor Interconnect is UltraPath Interconnect (UPI), QuickPath Interconnect (QPI), Advanced Microcontroller Bus Architecture (AMBA), Infinity Fabric, or Peripheral Component Interconnect (PCI)-Express (PCIe).
6 . The compute node of claim 1 , wherein the circuitry includes a redirection table to store the action associated with the destination address.
7 . A server comprising:
a memory; and
a compute node to couple to the memory, the compute node comprising:
an interface to a network; and
two or more processors, a processor comprising:
a processor interconnect; and
circuitry to redirect, via a programmable processor-to-processor agent of the processor, a first packet received from an application to be transmitted to another application in another processor, the circuitry to redirect the first packet via the processor interconnect to the other application in the other processor based on an action associated with a destination address in the first packet;
wherein:
the programmable processor-to-processor agent is to exchange rule data with another programmable processor-to-processor agent of the other processor; and
the programmable processor-to-processor agent and the another programmable processor-to-processor agent are to implement packet redirection via the processor interconnect based, at least in part, upon the rule data.
8 . The server of claim 7 , wherein the circuitry to redirect a second packet received from the application via the interface to the network to the other application in the other processor.
9 . The server of claim 7 , wherein the action is to forward the first packet to the other application in the other processor.
10 . The server of claim 7 , wherein the Processor Interconnect is a point-to-point processor interconnect.
11 . The server of claim 10 , wherein the Point-to-Point Processor Interconnect is UltraPath Interconnect (UPI), QuickPath Interconnect (QPI), Advanced Microcontroller Bus Architecture (AMBA), Infinity Fabric, or Peripheral Component Interconnect (PCI)-Express (PCIe).
12 . The server of claim 7 , wherein the circuitry includes a redirection table to store the action associated with the destination address.
13 . A method comprising:
receiving, by circuitry in a compute node, a first packet from an application associated with a processor to be transmitted via a network to another application in another processor; and
redirecting, by the circuitry in the compute node, via a programmable processor-to-processor agent of the processor, the first packet via a processor interconnect to the other application in the other processor based on an action associated with a destination address in the first packet;
wherein:
the programmable processor-to-processor agent is to exchange rule data with another programmable processor-to-processor agent of the other processor; and
the programmable processor-to-processor agent and the another programmable processor-to-processor agent are to implement packet redirection via the processor interconnect based, at least in part, upon the rule data.
14 . The method of claim 13 , wherein the circuitry to redirect a second packet received from the application via the network to the other application in the other processor.
15 . The method of claim 13 , wherein the action is to forward the first packet to the other application in the other processor.
16 . The method of claim 15 , wherein the Processor Interconnect is a point-to-point processor interconnect.
17 . The method of claim 16 , wherein the Point-to-Point Processor Interconnect is UltraPath Interconnect (UPI), QuickPath Interconnect (QPI), Advanced Microcontroller Bus Architecture (AMBA), Infinity Fabric, or Peripheral Component Interconnect (PCI)-Express (PCIe).
18 . The method of claim 13 , further comprising:
storing the action associated with the destination address in a redirection table.
19 . One or more non-transitory machine-readable storage media storing a plurality of instructions that when executed, result in a compute node being configured to perform operations comprising:
receive a packet from an application associated with a processor to be transmitted via a network to another application in another processor; and
redirect the packet, via a processor interconnect and programmable processor-to-processor agents of the processor and the other processor, to the other application in the other processor based on an action associated with a destination address in the packet;
wherein:
the programmable processor-to-processor agents are to exchange rule data; and
the programmable processor-to-processor agents are to implement packet redirection via the processor interconnect based, at least in part, upon the rule data.
20 . The one or more non-transitory machine-readable storage media of claim 19 , wherein the plurality of instructions, when executed, further result in the compute node being configured to:
redirect a second packet received from the application via the network to the other application in the other processor.
21 . The one or more non-transitory machine-readable storage media of claim 19 , wherein the action is to forward the packet to the other application in the other processor.
22 . The one or more non-transitory machine-readable storage media of claim 19 , wherein the processor interconnect is a point-to-point processor interconnect.
23 . The one or more non-transitory machine-readable storage media of claim 22 , wherein the Point-to-Point Processor Interconnect is UltraPath Interconnect (UPI), QuickPath Interconnect (QPI), Advanced Microcontroller Bus Architecture (AMBA), Infinity Fabric, or Peripheral Component Interconnect (PCI)-Express (PCIe).
24 . The one or more non-transitory machine-readable storage media of claim 19 , wherein the plurality of instructions, when executed, further result in the compute node being configured to:
store the action associated with the destination address in a redirection table.