Multi-mode memory module and memory component
A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.
1 . A memory module comprising:
an address buffer circuit;
a command/address channel; and
a memory rank controlled by the address buffer circuit via the command/address channel, the memory rank including a plurality of memory components where each of the plurality of memory components comprises:
a respective plurality of memory component data ports;
a respective memory core to store data; and
a respective data interface to transfer data between the respective memory core and the respective plurality of memory component data ports, the respective data interface supporting a first data width mode in which the respective data interface transfers data at a first bit width via a first set of the respective plurality of memory component data ports, the respective data interface supporting a second data width mode in which the respective data interface transfers data at a second bit width via a second set of the respective plurality of memory component data ports; and
a plurality of memory module data pins to transfer the data between the respective plurality of memory component data ports and a memory controller.
2 . The memory module of claim 1 , wherein the first bit width is greater than the second bit width.
3 . The memory module of claim 1 , wherein in the first data width mode the respective data interface transfers the data at the first bit width and a first burst length, and in the second data width mode the respective data interface transfers the data at the second bit width and a second burst length that is different from the first burst length.
4 . The memory module of claim 3 , wherein the second burst length is longer than the first burst length.
5 . The memory module of claim 4 , wherein a product of the first bit width and the first burst length is equal to a product of the second bit width and the second burst length.
6 . The memory module of claim 5 , wherein the first bit width is eight bits and the first burst length is eight, and the second bit width is four bits and the second burst length is sixteen.
7 . The memory module of claim 1 , wherein each of the plurality of memory components further comprises:
a respective data path between the respective data interface and the respective memory core, the respective data path having a third bit width that is greater than the first bit width of the first data width mode and the second bit width of the second data width mode.
8 . The memory module of claim 7 , wherein in both the first data width mode and the second data width mode, the respective data interface writes data to the respective memory core via the respective data path.
9 . The memory module of claim 7 , wherein in both the first data width mode and the second data width mode, the respective data interface reads data from the respective memory core via the respective data path.
10 . The memory module of claim 1 , wherein the second set of the respective plurality of memory component data ports has less memory component data ports than the first set of the respective plurality of memory component data ports.
11 . The memory module of claim 1 , wherein the first set of the respective plurality of memory component data ports include first memory component data ports and second memory component data ports, and in the first data width mode the respective data interface transfers the data via the first memory component data ports and the second memory component data ports, and in the second data width mode the respective data interface transfers the data via the second set of the respective plurality of memory component data ports that includes the first memory component data ports but not the second memory component data ports.
12 . The memory module of claim 1 , wherein:
in a memory read operation of the first data width mode, the respective data interface is to transmit a first timing reference signal associated with a first portion of the first bit width, and is to transmit a second timing reference signal associated with a second portion of the first bit width; and
in a memory read operation of the second data width mode, the respective data interface is to transmit a timing reference signal associated with all bits of the second bit width.
13 . The memory module of claim 1 , wherein at least one of the plurality of memory components comprises a mode register to store a setting indicative of a data transfer width, and the respective data interface operates in the first data width mode or the second data width mode depending on the setting stored in the mode register.
14 . The memory module of claim 1 , wherein the respective plurality of memory component data ports included in the at least one of the plurality of memory components are shared with another memory component from the plurality of memory components.
15 . A memory module comprising:
a memory rank controlled by an address buffer circuit via a command/address channel, the memory rank including a plurality of memory components where each of the plurality of memory components comprises:
a respective plurality of memory component data ports;
a respective memory core to store data; and
a respective data interface to transfer data between the respective memory core and the respective plurality of memory component data ports, the respective data interface supporting a first data width mode in which the respective data interface transfers data at a first bit width via a first set of the respective plurality of memory component data ports, the respective data interface supporting a second data width mode in which the respective data interface transfers data at a second bit width via a second set of the respective plurality of memory component data ports; and
a plurality of memory module data pins to transfer the data between the respective plurality of memory component data ports and a memory controller.
16 . A memory module comprising:
address buffering means;
command/address communication means; and
a memory rank controlled by the address buffering means via the command/address communication means, the memory rank including a plurality of memory components where each of the plurality of memory components comprises:
a respective plurality of memory component data port means;
a respective memory storing means to store data; and
a respective data interfacing means to transfer data between the respective memory storing means and the respective plurality of memory component data port means, the respective data interfacing means supporting a first data width mode in which the respective data interfacing means transfers data at a first bit width via a first set of the respective plurality of memory component data port means, the respective data interfacing means supporting a second data width mode in which the respective data interfacing means transfers data at a second bit width via a second set of the respective plurality of memory component data port means; and
a plurality of memory module data connection means to transfer the data between the respective plurality of memory component data port means and a memory controller.