A/D converter control circuit

1 . An analog/digital (A/D) conversion control circuit comprising:

a scan group control unit controlling a plurality of A/D conversion channels with a plurality of scan groups having different priorities; and

a First In First Out (FIFO) unit provided to correspond to each of the plurality of scan groups, each FIFO unit having a plurality of FIFO memories that sequentially stores an output from the scan group control unit for each corresponding scan group,

wherein the scan group control unit includes:

an input reception unit receiving an A/D conversion channel of a corresponding scan group among the plurality of A/D conversion channels according to an instruction, and outputting the received A/D conversion channel to the corresponding FIFO memory, the input reception unit further receiving a conversion start trigger of the corresponding scan group, and outputting, to an arbitration unit, a control signal indicating that A/D conversion of the corresponding scan group is active, the control signal being asserted from a start of A/D conversion of the corresponding scan group until a last A/D conversion channel of the corresponding scan group is received, and outputting information indicating a rise and a fall of the control signal; and

the arbitration unit determining timing of conversion start, interruption, and restart in each of the plurality of scan groups based on the control signal and the information indicating the rise and the fall of the control signal,

wherein the FIFO unit further includes a plurality of pointer control units provided correspondingly to the plurality of FIFO memories, respectively,

wherein each of the plurality of pointer control units includes a clear timing selection register configured to select, from among the conversion start, the interruption, and the restart determined by the arbitration unit, at least one event as a pointer-clear timing, and a selector configured to output a clear timing selection signal based on information stored in the clear timing selection register,

wherein each of the pointer control units clears or changes a write pointer and a read pointer of the corresponding FIFO memory based on a determination signal output from the arbitration unit at the selected timing according to a priority of the corresponding scan group,

wherein each of the pointer control units includes a restoration buffer configured to store a position of the write pointer at the start of the corresponding scan group based on the determination signal, and to set the write pointer at the interruption and the restart of the corresponding scan group to a position corresponding to a value stored in the restoration buffer, and

wherein each corresponding FIFO memory performs a read processing by using the read pointer after the last A/D conversion channel of the corresponding scan group is stored.

2 . The A/D conversion control circuit according to claim 1 , wherein each FIFO memory has a number of stages set to an integral multiple of a total number of AD conversion channels included in the corresponding scan group.

3 . The A/D conversion control circuit according to claim 1 , wherein each of the pointer control units outputs a clear signal that clears or changes a position of a write pointer or a read pointer of the corresponding FIFO memory at the timing of at least one of the start, the interruption, and the restart of the corresponding scan group based on a combination of a timing signal output from the arbitration unit at times of conversion start, interruption, and restart by the corresponding scan group, and a clear timing selection signal.

4 . The A/D conversion control circuit according to claim 1 , wherein the arbitration unit determines timing of conversion start, interruption, and restart for each of the plurality of scan groups based on rise and fall of a conversion start trigger in corresponding scan group.