Systems and methods of testing memory devices
View Patent ↗A memory circuit includes a memory array comprising a first portion comprising a plurality of first memory cells, and a second portion comprising a plurality of second memory cells. The memory circuit includes an input/output (I/O) circuit physically disposed next to the memory array along a first lateral direction. The I/O circuit is operatively coupled to the first portion and the second portion through a first access line and a second access line, respectively. The memory circuit includes a first pre-charge circuit physically disposed opposite the first portion from the I/O circuit, and configured to charge the first access line prior to accessing the first memory cells. The memory circuit includes a second pre-charge circuit physically disposed opposite the second portion from the first pre-charge circuit, and configured to charge at least a portion of the second access line prior to accessing the second memory cells.
1 . A method for testing a memory device, comprising:
providing a plurality of test structures, wherein each of the plurality of test structures is physically disposed next to a corresponding one of memory sub-arrays, wherein each of the plurality of test structures is configured to emulate a plurality of interconnect structures that electrically couple a plurality of word lines (WLs) of the corresponding memory sub-array to a driver circuit, and
the plurality of test structures are connected in series;
determining whether a level of current conducting through the serially connected test structures satisfies a condition; and
testing, based on the determination, one of the plurality of test structures by bypassing the rest of the plurality of test structures at a time.
2 . The method of claim 1 , wherein each of the plurality of test structures comprises a plurality of vertical test interconnect structures that emulate a corresponding one of the plurality of interconnect structures.
3 . The method of claim 2 , wherein the plurality of vertical test interconnect structures each vertically extends through a corresponding one of the plurality of test structures with a same height.
4 . The method of claim 2 , wherein the plurality of vertical test interconnect structures are electrically coupled to one another in series through a first plurality of horizontally extending interconnect structures and a second plurality of horizontally extending interconnect structures.
5 . The method of claim 4 , wherein the first plurality of horizontally extending interconnect structures and the second plurality of horizontally extending interconnect structures are disposed along a top surface and a bottom surface of the plurality of vertical test interconnect structures, respectively.
6 . The method of claim 1 , wherein determining whether the level of current satisfies the condition comprises:
determining that the condition is satisfied based on the level of current conducting through the serially connected test structures being less than a threshold.
7 . The method of claim 6 , further comprising:
determining, in response to determining that the condition is satisfied, a presence of an open circuit along a conduction path of at least one of the plurality of test structures, indicative of a presence of an open circuit in at least one of the plurality of interconnect structures of the corresponding memory sub-array.
8 . The method of claim 1 , wherein the plurality of test structures comprises a first test structure and a second test structure disposed next to a first memory sub-array of the memory sub-arrays and a third test structure and a fourth test structure disposed next to a second memory sub-array of the memory sub-arrays, wherein the second test structure is connected serially to a first switch and in parallel to a second switch, and wherein the fourth test structure is connected serially to a third switch and in parallel to a fourth switch.
9 . The method of claim 8 , wherein the second switch is configured to bypass the first and second test structures, and wherein the fourth switch is configured to bypass the third and fourth test structures.
10 . The method of claim 8 , wherein bypassing the rest of the plurality of test structures comprises:
alternately activating the second switch with respect to the first switch to selectively bypass the first memory sub-array at a first time; and
alternately activating the fourth switch with respect to the third switch to selectively bypass the second memory sub-array at a second time.
11 . The method of claim 8 , wherein the first through fourth test structures are electrically coupled to one another in series.
12 . A non-transitory computer-readable medium having stored thereon computer executable instructions, the computer executable instructions being executable by at least one processor to perform a method comprising testing a memory device including:
determining that a level of current conducting through a plurality of serially connected test structures satisfies a condition, wherein each of the plurality of serially connected test structures includes a first test structure and a second test structure coupled in series, each of the first and second test structures is disposed next to a corresponding one of memory blocks, and each of the first and second test structures is configured to emulate a plurality of interconnect structures that electrically couple a plurality of word lines (WLs) of the corresponding memory block to a driver circuit; and
bypassing, in response to the determination, one or more of a plurality of test structures at a time to test at least the first and second test structures.
13 . The non-transitory computer-readable medium of claim 12 , wherein the plurality of WLs of the corresponding memory block are formed as a staircase, and wherein the plurality of interconnect structures are laterally spaced from the staircase.
14 . The non-transitory computer-readable medium of claim 12 , wherein each of the plurality of test structures comprises a plurality of vertical test interconnect structures that emulate a corresponding one of the plurality of interconnect structures, and wherein the plurality of vertical test interconnect structures each vertically extends through a corresponding one of the plurality of test structures with a same height.
15 . The non-transitory computer-readable medium of claim 14 , wherein the plurality of vertical test interconnect structures are electrically coupled to one another in series through a first plurality of horizontally extending interconnect structures and a second plurality of horizontally extending interconnect structures, and wherein the first plurality of horizontally extending interconnect structures and the second plurality of horizontally extending interconnect structures are disposed along a top surface and a bottom surface of the plurality of vertical test interconnect structures, respectively.
16 . The non-transitory computer-readable medium of claim 12 , wherein determining that the level of current satisfies the condition, the method includes:
detecting the level of current conducting through the serially connected test structures; and
determining that the condition is satisfied in response to the level of current being less than a threshold,
wherein satisfying the condition indicates a presence of an open circuit along a conduction path of at least one of the plurality of test structures, indicative of a presence of an open circuit in at least one of the plurality of interconnect structures of the corresponding memory block.
17 . The non-transitory computer-readable medium of claim 12 , wherein the first test structure and the second test structure are disposed next to a first memory block of the memory blocks and a third test structure and a fourth test structure are disposed next to a second memory block of the memory blocks, wherein the second test structure is connected serially to a first switch and in parallel to a second switch configured to bypass the first and second test structures, and wherein the fourth test structure is connected serially to a third switch and in parallel to a fourth switch configured to bypass the third and fourth test structures.
18 . A memory device, comprising:
a plurality of memory sub-arrays; and
a plurality of test structures coupled in series, wherein each of the plurality of test structures is physically disposed next to a corresponding one of the plurality of memory sub-arrays, each of the plurality of test structures is configured to emulate a plurality of interconnect structures that electrically couples a plurality of word lines (WLs) of the corresponding memory sub-array to a driver circuit, wherein the plurality of test structures are configured to
determine whether a level of current conducting through the serially connected test structures satisfies a condition, and
responsive to the level of current satisfying the condition, test one of the plurality of test structures by bypassing the rest of the plurality of test structures at a time.
19 . The memory device of claim 18 , further comprising:
a plurality of vertical test interconnect structures that emulate a corresponding one of the plurality of interconnect structures, wherein the plurality of vertical test interconnect structures each vertically extends through a corresponding one of the plurality of test structures with a same height, wherein the plurality of vertical test interconnect structures are electrically coupled to one another in series through a first plurality of horizontally extending interconnect structures and a second plurality of horizontally extending interconnect structures, and wherein the first plurality of horizontally extending interconnect structures and the second plurality of horizontally extending interconnect structures are disposed along a top surface and a bottom surface of the plurality of vertical test interconnect structures, respectively.
20 . The memory device of claim 18 , wherein the plurality of test structures comprises a first test structure and a second test structure disposed next to a first memory sub-array of the plurality of memory sub-arrays and a third test structure and a fourth test structure disposed next to a second memory sub-array of the plurality of memory sub-arrays, the memory device further comprises:
a first switch serially connected to the second test structure;
a second switch connected in parallel to the second test structure, configured to bypass the first and second test structures by alternately activating the first and second switches so as to selectively bypass the first and second test structures;
a third switch serially connected to the fourth test structure; and
a fourth switch connected in parallel to the fourth test structure, configured to bypass the third and fourth test structures by alternately activating the third and fourth switches so as to selectively bypass the third and fourth test structures.