Apparatuses and methods

1 . An apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to:

determine that a first composite link of a plurality of composite peripheral component interconnect express (PCIe) links terminating at the same PCIe root port lacks support for enabling a desired power saving state or an exit latency for the first composite link is above a first latency threshold;

determine whether an exit latency for a second composite link of the plurality of composite PCIe links is below a second latency threshold; and

selectively trigger at least one sub-link of the second composite link to enable the desired power saving state if the exit latency for the second composite link is below the second latency threshold.

2 . The apparatus of claim 1 , wherein the first threshold is based on a maximal exit latency accepted by an endpoint of the first composite link, and wherein the second latency threshold is based on a maximal exit latency accepted by an endpoint of the second composite link.

3 . The apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to selectively trigger at least one of the sub-link and a further sub-link of the second composite link to disable the desired power saving state or a further power saving state if it is determined that the exit latency is above the second latency threshold.

4 . The apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to:

determine whether an updated exit latency for the second composite link is below the second latency threshold after selectively triggering the sub-link to enable the desired power saving state; and

selectively trigger the sub-link to disable the desired power saving state if it is determined that the updated exit latency is above the second latency threshold.

5 . The apparatus of claim 4 , wherein the machine-readable instructions comprise instructions to selectively trigger a further sub-link of the second composite link to enable the desired power saving state if it is determined that the updated exit latency is below the second latency threshold.

6 . The apparatus of claim 4 , wherein the machine-readable instructions comprise instructions to selectively trigger the sub-link or the further sub-link to enable a further power saving state if it is determined that the updated exit latency is below the second latency threshold.

7 . The apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to determine whether the sub-link supports enabling the desired power saving state, wherein the sub-link is selectively triggered to enable the desired power saving state if it is determined that the sub-link supports enabling the desired power saving state.

8 . The apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to determine whether an exit latency for the sub-link is above an exit latency for at least one further sub-link of the second composite link upstream of the sub-link, wherein the sub-link is selectively triggered to enable the desired power saving state if it is determined that the exit latency for the sub-link is above the exit latency for the further sub-link.

9 . The apparatus of claim 8 , wherein the machine-readable instructions comprise instructions to selectively trigger the further sub-link to disable the desired power saving state or a further power saving state if it is determined that the exit latency for the sub-link is below the exit latency for the further sub-link.

10 . The apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to:

selectively trigger iteratively, for each sub-link of a plurality of sub-links of the second composite link, said sub-link to enable the desired power saving state;

determine, in each iteration, whether an updated exit latency for the second composite link is below the second threshold after selectively triggering said sub-link to enable the desired power saving; and

selectively trigger said sub-link to disable the desired power saving state if it is determined that the updated exit latency is above the second latency threshold.

11 . The apparatus of claim 10 , wherein the machine-readable instructions comprise instructions to:

determine, in each iteration, whether an exit latency for said sub-link is above an exit latency for at least one further sub-link of the plurality of sub-links upstream to said sub-link; and

selectively trigger at least one of said sub-link and the further sub-link to disable the desired power saving state or a further power saving state if it is determined that the exit latency for the sub-link is below the exit latency for the further sub-link.

12 . The apparatus of claim 1 , further comprising memory circuitry to store, for each sub-link of the plurality of composite links, an indication whether said sub-link has been triggered to enable or disable the desired power saving state.

13 . The apparatus of claim 1 , wherein the machine-readable instructions comprise instructions to:

selectively trigger iteratively, for each power saving state of a plurality of power saving states comprising the desired power saving state, the sub-link to enable said power saving state;

determine, in each iteration, whether an updated exit latency for the second composite link is below the second threshold after selectively triggering said sub-link to enable said power saving state; and

selectively trigger said sub-link to disable said power saving state if it is determined that the updated exit latency is above the second latency threshold.

14 . An apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to:

determine that a composite peripheral component interconnect express (PCIe) link lacks support for enabling a desired power saving state or an exit latency for the composite link is above a latency threshold;

determine that an exit latency of the composite link, with a first subset of sub-links having enabled the desired power saving state and a second subset of sub-links having disabled the desired power saving state, is below the latency threshold and that the first subset supports enabling the desired power saving state; and

selectively trigger at least one sub-link of the first subset to enable the desired power saving state.

15 . The apparatus of claim 14 , wherein the threshold is based on a maximal exit latency accepted by an endpoint of the composite link.

16 . The apparatus of claim 14 , wherein the machine-readable instructions comprise instructions to determine whether an exit latency for the sub-link is above an exit latency for at least one further sub-link of the composite link upstream of the sub-link, wherein the sub-link is selectively triggered to enable the desired power saving state if it is determined that the exit latency for the sub-link is above the exit latency for the further sub-link.

17 . The apparatus of claim 16 , wherein the machine-readable instructions comprise instructions to selectively trigger the further sub-link to disable the desired power saving state or a further power saving state if it is determined that the exit latency for the sub-link is below the exit latency for the further sub-link.

18 . The apparatus of claim 14 , wherein the machine-readable instructions comprise instructions to determine the first subset and the second subset by:

determining for each sub-link of a plurality of sub-links of the composite link, whether said sub-link supports enabling the desired power saving state;

if it is determined that said sub-link supports enabling the desired power saving state, selectively triggering said sub-link to enable the desired power saving state;

determining, after selectively triggering said sub-link to enable the desired power saving state, whether an exit latency for the composite link is below the latency threshold;

if it is determined that the exit latency is below the latency threshold, allocating said sub-link to the first subset.

19 . The apparatus of claim 14 , further comprising memory circuitry to store, for each sub-link of a plurality of sub-links of the composite link, an indication whether said sub-link has been triggered to enable or disable the desired power saving state.

20 . The apparatus of claim 14 , wherein the machine-readable instructions comprise instructions to:

determine that an exit latency of the composite link, with a third subset of sub-links having enabled a further power saving state, is below the latency threshold and that the third subset supports enabling the further power saving state; and

selectively trigger at least one sub-link of the third subset to enable the further power saving state.

21 . The apparatus of claim 14 , wherein the machine-readable instructions comprise instructions to:

determine that a second composite PCIe link, terminating at the same PCIe root complex like the composite link, lacks support for enabling a desired power saving state or an exit latency for the second composite link is above a second latency threshold;

determine that an exit latency of the second composite link, with a third subset of sub-links having enabled the desired power saving state and a fourth subset of sub-links having disabled the desired power saving state, is below the second latency threshold and that the third subset supports enabling the desired power saving state; and

selectively trigger at least one sub-link of the third subset to enable the desired power saving state.

22 . A method, comprising:

determining that a first composite link of a plurality of composite peripheral component interconnect express (PCIe) links terminating at the same PCIe root port lacks support for enabling a desired power saving state or an exit latency for the first composite link is above a first latency threshold;

determining whether an exit latency for a second composite link of the plurality of composite PCIe links is below a second latency threshold; and

selectively triggering at least one sub-link of the second composite link to enable the desired power saving state if the exit latency for the second composite link is below the second latency threshold.

23 . A method, comprising:

determining that a composite peripheral component interconnect express (PCIe) link lacks support for enabling a desired power saving state or an exit latency for the composite link is above a latency threshold;

determining that an exit latency of the composite link, with a first subset of sub-links having enabled the desired power saving state and a second subset of sub-links having disabled the desired power saving state, is below the latency threshold and that the first subset supports enabling the desired power saving state; and

selectively triggering at least one sub-link of the first subset to enable the desired power saving state.

24 . A non-transitory machine-readable storage medium including program code, when executed, to cause a machine to perform the method of claim 22 .

25 . A non-transitory machine-readable storage medium including program code, when executed, to cause a machine to perform the method of claim 23 .