Processors, methods, systems, and instructions to select and store data elements from two source two-dimensional arrays indicated by permute control elements in a result two-dimensional array
Techniques for permuting two source two dimensional (2D) arrays are described. A processor of an aspect includes a decoder circuitry to decode an instruction having an opcode. The instruction may indicate a first source 2D array, a second source 2D array, and permute control elements. Execution circuitry is coupled with the decoder circuitry. The execution circuitry is to execute the decoded instruction to select data elements, from among any data elements of the first source 2D array, and any data elements of the second source 2D array, that are each indicated by a different corresponding one of the permute control elements. The execution circuitry is also to store the selected data elements in data element positions of a result 2D array that each correspond to a different one of the permute control elements. Other processors, methods, systems, and instructions are disclosed.
1 . A processor comprising:
a decoder circuitry to decode an instruction having an opcode, the instruction to indicate a first source two-dimensional (2D) array of data elements arranged in a plurality of rows and a plurality of columns, a second source 2D array of data elements arranged in a plurality of rows and a plurality of columns, and a plurality of permute control elements; and
execution circuitry coupled with the decoder circuitry, the execution circuitry to perform operations corresponding to the instruction, including to:
select a plurality of single data elements, from among any of the data elements of the first source 2D array of data elements, and any of the data elements of the second source 2D array of data elements, wherein every selected single data element of the selected plurality of single data elements is to be selected by a different corresponding one of the plurality of permute control elements; and
store the selected plurality of single data elements in a plurality of single data element positions of a result 2D array, each and all of the single data element positions of the result 2D array to correspond to a different one of the plurality of permute control elements.
2 . The processor of claim 1 , wherein each of the plurality of permute control elements selects no more than a single data element the first source 2D array or the second source 2D array.
3 . The processor of claim 1 , wherein the plurality of permute control elements includes a same number of permute control elements as a number of the plurality of single data elements positions of the result 2D array.
4 . The processor of claim 1 , wherein each of the data elements of the first source 2D array of data elements is a single integer data element or a single floating-point data element, and wherein the decoder circuitry is to decode the instruction that is to indicate a third source 2D array of the plurality of permute control elements arranged in a plurality of rows and a plurality of columns, and wherein the result 2D array has a same number of rows as a number of rows of the third source 2D array and the result 2D array has a same number of columns as a number of columns of the third source 2D array.
5 . The processor of claim 1 , wherein each row of the first source 2D array has a plurality of data elements, wherein each column of the first source 2D array has a plurality of data elements, and wherein the decoder circuitry is to decode the instruction that is to indicate one of a plurality of sequential vector registers that are to store the plurality of permute control elements.
6 . The processor of claim 1 , wherein the decoder circuitry is to decode the instruction that is to indicate a single vector register that is to store the plurality of permute control elements.
7 . The processor of claim 6 , wherein the single vector register comprises at least 512-bits and is to store 8-bit permute control elements, and wherein the first and second source 2D arrays together are to have no more than 256 data elements.
8 . The processor of claim 1 , wherein the decoder circuitry is to decode the instruction that is to indicate a memory location that is to store the plurality of permute control elements.
9 . The processor of claim 1 , wherein each of the data elements of the first source 2D array of data elements is a single integer value or a single floating-point value, wherein the first source 2D array has at least eight rows and at least eight columns, wherein each of the rows of the first source 2D array has at least eight data elements, wherein each of the columns of the first source 2D array has at least eight data elements, and further comprising a register to store configuration information, the configuration information to configure a number of the rows of the first source 2D array, and a number of the columns of the first source 2D array.
10 . The processor of claim 1 , further comprising a plurality of physical registers, and wherein one or more of the first and second source 2D arrays are to be stored in a tile register, the tile register comprising an overlay over the physical registers.
11 . A method performed by a processor comprising:
decoding an instruction having an opcode, the instruction indicating a first source two-dimensional (2D) array of data elements arranged in a plurality of rows and a plurality of columns, a second source 2D array of data elements arranged in a plurality of rows and a plurality of columns, and a plurality of permute control elements; and
performing operations corresponding to the instruction, including:
selecting a plurality of single data elements, from among any of the data elements of the first source 2D array of data elements, and any of the data elements of the second source 2D array of data elements, wherein every selected single data element of the selected plurality of single data elements is to be selected by a different corresponding one of the plurality of permute control elements; and
storing the selected plurality of single data elements in a plurality of single data element positions of a result 2D array, each and all of the single data element positions of the result 2D array to correspond to a different one of the plurality of permute control elements.
12 . The method of claim 11 , wherein each of the plurality of permute control elements selects no more than a single data element the first source 2D array or the second source 2D array, and wherein the plurality of permute control elements includes a same number of permute control elements as a number of the plurality of single data elements positions of the result 2D array.
13 . The method of claim 11 , wherein the decoding is by decoder circuitry that is to decode the instruction that is to indicate a third source 2D array that is to store the plurality of permute control elements.
14 . The method of claim 11 , wherein the decoding is by decoder circuitry that is to decode the instruction that is to indicate one of a plurality of sequential vector registers that are to store the plurality of permute control elements.
15 . The method of claim 11 , wherein the decoding is by decoder circuitry that is to decode the instruction that is to indicate a single vector register that is to store the plurality of permute control elements.
16 . The method of claim 11 , further comprising a register to store configuration information, the configuration information to configure a number of row of the first source 2D array, and a number of columns of the first source 2D array.
17 . The method of claim 11 , wherein the first source 2D array has an array of data elements arranged in at least eight rows and at least eight columns, wherein each row of the first source 2D array has at least eight data elements, wherein each column of the first source 2D array has at least eight data elements.
18 . A system comprising:
an interconnect;
a processor coupled with the interconnect, the processor to receive an instruction having an opcode, the instruction to indicate a first source two-dimensional (2D) array of data elements arranged in a plurality of rows and a plurality of columns, a second source 2D array of data elements arranged in a plurality of rows and a plurality of columns, and a plurality of permute control elements, the processor, to perform operations corresponding to the instruction, including to:
select a plurality of single data elements, from among any of the data elements of the first source 2D array of data elements, and any of the data elements of the second source 2D array of data elements, wherein every selected single data element of the selected plurality of single data elements is to be selected by a different corresponding one of the plurality of permute control elements; and
store the selected plurality of single data elements in a plurality of single data element positions of a result 2D array, each and all of the single data element positions of the result 2D array to correspond to a different one of the plurality of permute control elements; and
a dynamic random access memory (DRAM) coupled with the interconnect.
19 . The system of claim 18 , further comprising a mass storage device coupled with the processor, wherein each of the plurality of data elements that is selected is a single integer value or a single floating-point value, and wherein the processor comprises decoder circuitry to decode the instruction that is to indicate a third source 2D array that is to store the plurality of permute control elements.
20 . The system of claim 18 , further comprising a peripheral component interconnect express (PCIe) interface coupled with the processor, and wherein the processor comprises decoder circuitry to decode the instruction that is to indicate a single vector register that is to store the plurality of permute control elements.