Efficient exception handling in trusted execution environments

1 . A hardware processor comprising:

a register having a field set to enable an architecturally protected execution environment at one of a plurality of contexts for code in an architecturally protected enclave in memory;

a decoder to decode a single instruction having a format including a first field for an opcode, the opcode to indicate execution circuitry is to perform a context change; and

the execution circuitry to perform one or more operations corresponding to the single instruction, the one or more operations including:

decrementing an index to an array of save areas, each save area corresponding to a different context, wherein the index is used to select a save area for a corresponding context in the array of save areas to store a state for the corresponding context in response to an enclave exiting event encountered by the architecturally protected enclave; and

changing, within the architecturally protected enclave, from a first context to a second context, wherein the state of the second context is provided from the corresponding context in the array of save areas.

2 . The hardware processor of claim 1 , wherein:

the hardware processor is to operate in a first mode and a second mode;

in response to a second enclave exiting event in the second mode, the hardware processor is to cause a next enclave entry to be into the first context; and

in the first context, the hardware processor is to apply one or more mitigations against an attack.

3 . A method comprising:

enabling an architecturally protected execution environment for code executing in an architecturally protected enclave in memory in response to a field of a register of a hardware processor being set;

decoding a single instruction having a format including a first field for an opcode, the opcode to indicate execution circuitry of the hardware processor is to perform a context change;

encountering, by the architecturally protected enclave, an enclave exiting event; and

performing, by the execution circuitry, one or more operations corresponding to the single instruction, the one or more operations including:

decrementing an index to an array of save areas, each save area corresponding to a different context, wherein the index is used to select a save area for a corresponding context in the array of save areas to store a state for the corresponding context in response to the enclave exiting event; and

changing, within the architecturally protected enclave, from one context of a plurality of contexts to an other context of the plurality of contexts, wherein the state of the other context is provided from the corresponding context in the array of save areas.

4 . The method of claim 3 , further comprising, before decoding the single instruction:

entering the architecturally protected enclave in the other context; and

exiting the architecturally protected enclave in response to the enclave exiting event.

5 . The method of claim 4 , wherein exiting the architecturally protected enclave includes saving the other context in the save area in the array of save areas.

6 . The method of claim 5 , further comprising, after exiting the architecturally protected enclave, re-entering the architecturally protected enclave in the one context to handle the enclave exiting event.

7 . The method of claim 6 , further comprising invoking, by an exception handler in the one context, the single instruction.

8 . The method of claim 3 , wherein the one or more operations also include restoring the state of the other context.

9 . The method of claim 3 , further comprising, before invoking the single instruction, restoring, by software, the state of the other context.

10 . A system comprising:

a memory to store an architecturally protected enclave; and

a processor including:

a register having a field set to enable an architecturally protected execution environment for code in the architecturally protected enclave;

a decoder to decode a single instruction having a format including a first field for an opcode, the opcode to indicate execution circuitry is to perform a context change; and

the execution circuitry to perform one or more operations corresponding to the single instruction, the one or more operations including:

decrementing an index to an array of save areas, each save area corresponding to a different context, wherein the index is used to select a save area for a corresponding context in the array of save areas to store a state for the corresponding context in response to an enclave exiting event encountered by the architecturally protected enclave; and

changing, within the architecturally protected enclave, from a first context to a second context, wherein the state of the second context is provided from the corresponding context of the save area, referenced by the index, in the architecturally protected enclave in the memory.