IP Library Granted Patent US 12699826
Granted Patent B2
US 12699826 · App. 17/902,810 · Granted Aug 4, 2026

Power prediction and circuit design methods

Inventors: Nicolas Christophe Hébert (Valbonne, FR); Shidhartha Das (Upper Cambourne, GB)
Assignee: Arm Limited
G06F30/327G06F30/27G06F30/3308
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12699826
App. No.
17/902,810
Granted
Aug 4, 2026
Kind
B2
Abstract

According to one implementation of the present disclosure, a method includes: receiving, by a hardware design generation circuit, a plurality of input signals of a software workload on a processing unit; training a power prediction model based on a toggling of the input signals accumulated over a training interval range; determining, by the hardware design generation circuit, a plurality of prediction proxies and respective weightings for the plurality of prediction proxies based at least partially on the trained power prediction model, wherein the plurality of weighted prediction proxies correspond to a power output of the hardware design generation circuit; and generating an updated circuit design of the processing unit based on the power output.

Claims (25)

1 . A method comprising:

receiving, by a hardware design generation circuit, a plurality of input signals of a software workload on a processing unit;

training a power prediction model based on a toggling of the input signals accumulated over a training interval range;

determining, by the hardware design generation circuit, a plurality of prediction proxies and respective weightings for the plurality of prediction proxies based at least partially on the trained power prediction model;

generating, by the hardware design generation circuit, a power output; and

generating an updated circuit design of the processing unit based on the power output.

2 . The method of claim 1 , wherein the power prediction model is trained by a power simulation of the processing unit.

3 . The method of claim 1 , wherein the updated circuit design is generated by a synthesis tool of a computing device.

4 . The method of claim 1 , further comprising:

generating, by a computation differentiation circuitry, a differential power output based on the power output, wherein the differential power output corresponds to a rate of change of the power output.

5 . The method of claim 4 , further comprising:

generating, by a synthesis tool, the updated circuit design based on the differential power output.

6 . The method of claim 1 , wherein the software workload simulation is designed to generate power output of a plurality of register-transfer level (RTL) signals in simulation, and wherein the plurality of RTL signals corresponds to the input data signals, and wherein the plurality of weighted prediction proxies correspond to a power output of the hardware design generation circuit.

7 . The method of claim 1 , wherein the training interval range comprises a range of one or more clock cycles of a power simulation of the processing unit.

8 . The method of claim 1 , wherein training the power prediction model, by executing instructions corresponding to a power prediction modeling software stored on a computing device, comprises:

generating respective toggle data signals, by one or more toggle generators of the hardware design generation circuit, from the input signals, wherein the input signals correspond to a plurality of register-transfer level (RTL) signals in simulation; and

toggling, by the one or more toggle generators of the hardware design generation circuit, the toggle data signals at each clock cycle of the training interval range.

9 . The method of claim 8 , wherein determining the plurality of prediction proxies and the respective weightings of the plurality of prediction proxies, by executing the instructions corresponding to the power prediction modeling software stored on the computing device, comprise:

combining or not combining, by respective multiplexers and an adder, the toggled data signals based on a set of trainable weight values over the training interval range;

identifying, by the power prediction model, a subset of the of the plurality of RTL signals comprising non-zero weight terms, wherein the subset of the of the plurality of RTL signals correspond to a plurality of candidate prediction proxies;

toggling the plurality of candidate prediction proxies; and

combining or not combining, by the respective multiplexers and the adder, the plurality of candidate prediction proxies based on a second set of trainable weight values over each clock cycle of the training interval range.

10 . The method of claim 9 , wherein the toggled data signals are combined or not combined based on a correlation of predicted power being above a predicted power threshold, and wherein the plurality of candidate prediction proxies are combined or not combined based on a correlation of the prediction proxies being above a proxy threshold.

11 . The method of claim 1 , wherein training the power prediction model is based on one or more of a combination of a minimax concave penalty (MCP) algorithm, a pruning training model, a loss function equation, or a sparce linear model.

12 . The method of claim 1 , wherein the toggling of the input signals in a first clock cycle and respective power consumption is used as ground truth to train the power prediction model.