Modeling of four-state-aware content-addressable memories in an emulation system
The systems and methods described herein include an emulation system for modeling user integrated circuit (IC) designs having content-addressable memory (CAM) or ternary content-addressable memory (TCAM) design elements. The emulator includes compiling software performing synthesis and compiling operations that compile netlist logic for IC designs, including virtual instrumentation logic for handling administrative overhead functions. For a CAM/TCAM instance of the IC design, the emulator instantiates a wrapper comprising instrumentation logic that performs translation or transformation functions on inputs into the CAM/TCAM and on outputs produced from the CAM/TCAM, facilitating compatibility. The wrapper logic includes logic for modeling a CAM/TCAM search of the memory locations, including table-matching logic for comparing search query bits against the memory locations. The wrapper may further include error-handling logic for generating error messages in circumstances when the emulator or the IC design cannot handle the output of the CAM/TCAM.
1 . A system for emulating circuit designs including ternary content-addressable memories (TCAMs), the system comprising:
a set of emulator hardware for emulating a circuit design that is configured to operate with an unknown logic state, including a plurality of emulation processors for modeling a plurality of user-design circuits according to a netlist of the circuit design, and a plurality of physical binary memories for modeling one or more user-design TCAMs according to the netlist; and
a computing processor configured to:
identify, in the netlist for the circuit design, netlist logic for modeling a user-design TCAM using a physical binary memory of the emulator hardware;
instantiate a wrapper for the user-design TCAM, the wrapper comprising wrapper logic for modeling a search function of the user-design TCAM; and
merge the wrapper into the netlist by including the wrapper logic for the user-design TCAM around the netlist logic for the user-design TCAM of the netlist.
2 . The system according to claim 1 , wherein the wrapper logic is configured to model the search function using a mask and a query pattern.
3 . The system according to claim 1 , wherein the wrapper logic models the search function according to a matching-logic table.
4 . The system according to claim 1 , wherein the wrapper logic is configured to, for each TCAM address of a plurality TCAM addresses, output one or more bits indicating a comparison-result between a query pattern and content data stored in the TCAM address.
5 . The system according to claim 4 , wherein the wrapper logic is configured to output the comparison-result indicating no-match when the content data includes the unknown logic state.
6 . The system according to claim 4 , wherein the wrapper logic is configured to output the comparison-result indicating a match when the content data includes a wildcard logic state.
7 . The system according to claim 4 , wherein the wrapper logic is configured to output the comparison-result indicating no-match when the query pattern includes the unknown logic state.
8 . The system according to claim 1 , wherein the wrapper logic is further configured to model the user-design TCAM by performing one or more transformations of input ternary logic signals at one or more input ports of the user-design TCAM.
9 . The system according to claim 1 , wherein the wrapper logic is further configured to model the user-design TCAM by performing one or more transformations of one or more output logic signals at one or more output ports of the user-design TCAM.
10 . The system according to claim 1 , wherein the wrapper logic is further configured to output an error message in response to an unknown value at a port of the user-design TCAM.
11 . A computer-implemented method for emulating circuit designs including ternary content-addressable memories (TCAMs), the method comprising:
obtaining, by a computer, a netlist for a circuit design that operates with an unknown state and having one or more user-design ternary content-addressable memories (TCAMs) to be modeled according to the netlist using a plurality of physical binary memories of emulator hardware;
identifying, by the computer, netlist logic of the netlist for modeling a user-design TCAM of the one or more user-design TCAMs;
instantiating, by the computer, a wrapper for the user-design TCAM, the wrapper including wrapper logic for modeling a search function of the user-design TCAM; and
merging, by the computer, the wrapper into the netlist, by including the wrapper logic for the user-design TCAM around the netlist logic for the user-design TCAM.
12 . The method according to claim 11 , wherein the wrapper logic models the search function of a plurality of TCAM addresses of the user-design TCAM using a mask and a query pattern.
13 . The method according to claim 11 , wherein the wrapper logic models the search function according to a matching-logic table.
14 . The method according to claim 11 , wherein the wrapper logic, for each TCAM address of a plurality TCAM addresses, outputs one or more bits indicating a comparison-result between a query pattern and content data stored in the TCAM address.
15 . The method according to claim 14 , wherein the wrapper logic outputs the comparison-result indicating no-match when the content data includes the unknown logic state.
16 . The method according to claim 14 , wherein the wrapper logic outputs the comparison-result indicating a match when the content data includes a wildcard logic state.
17 . The method according to claim 14 , wherein the wrapper logic outputs the comparison-result indicating no-match when the query pattern includes the unknown logic state.
18 . The method according to claim 11 , wherein the wrapper logic models the user-design TCAM by performing one or more transformations of input ternary logic signals at one or more input ports of the user-design TCAM.
19 . The method according to claim 11 , wherein the wrapper logic models the user-design TCAM by performing one or more transformations of one or more output logic signals at one or more output ports of the user-design TCAM.
20 . The method according to claim 11 , wherein the wrapper logic outputs an error message in response to an unknown value at a port of the user-design TCAM.