IP Library › Granted Patent US 12699829
Granted Patent B2
US 12699829 · App. 17/984,053 · Granted Aug 4, 2026

Methods and apparatus to generate circuit timing constraint predictions using machine learning

Inventors: Lekshmi C (Bangalore, IN); Sourav Saha (Bangalore, IN); Anmol Khatri (Bangalore, IN); Raj Chetan Yadav (Vadodara, IN); Rakshit Bazaz (Bangalore, IN); Shivangi Gupta (Hosur, IN)
Assignee: Intel Corporation
G06F30/3312G06F2119/08
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Quick Facts
Patent No.
US 12699829
App. No.
17/984,053
Granted
Aug 4, 2026
Kind
B2
Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for methods and apparatus to generate I/O timing constraint predictions for system-on-chips using machine learning. An apparatus is disclosed herein comprising at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to extract delay features from a first system-on-chip design and a second system-on-chip design, apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design, compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design, and update the second system-on-chip design based on the error determined for the first system-on-chip design.

Claims (43)

1 . An apparatus comprising:

at least one memory;

machine readable instructions; and

processor circuitry to at least one of instantiate or execute the machine readable instructions to:

extract delay features from a first system-on-chip design and a second system-on-chip design;

apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design;

compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design; and

update timing constraints of the second system-on-chip design based on the error determined for the first system-on-chip design.

2 . The apparatus of claim 1 , wherein the processor circuitry is further to generate the machine learning model.

3 . The apparatus of claim 2 , wherein the processor circuitry is further to determine a learning algorithm for the machine learning model.

4 . The apparatus of claim 2 , wherein the processor circuitry is further to establish a timing path for the machine learning model.

5 . The apparatus of claim 2 , wherein the processor circuitry is further to establish a decision tree for the machine learning model.

6 . The apparatus of claim 2 , wherein the processor circuitry is to generate the machine learning model by using a chosen learning algorithm, a timing path, and a decision tree.

7 . The apparatus of claim 1 , wherein the processor circuitry is further to update the machine learning model based on the error determined of the first system-on-chip design.

8 . The apparatus of claim 7 , wherein the processor circuitry is further to modify a feature scale of the machine learning model.

9 . The apparatus of claim 7 , wherein the processor circuitry is further to modify a hyperparameter of the machine learning model.

10 . The apparatus of claim 7 , wherein the processor circuitry is further to remove a redundant feature from the machine learning model.

11 . The apparatus of claim 7 , wherein the processor circuitry is further to add a new feature to the machine learning model.

12 . The apparatus of claim 1 , wherein the second system-on-chip design is housed in a database.

13 . The apparatus of claim 1 , wherein the processor circuitry is further to output the error determined of the first system-on-chip design.

14 . A method to generate input-output timing constraints for a system-on-chip comprising:

extracting delay features from a first system-on-chip design and a second system-on-chip design;

applying a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design;

comparing the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design; and

updating timing constraints of the second system-on-chip design based on the error determined for the first system-on-chip design.

15 . An apparatus to generate input-output timing constraints for a system-on-chip comprising:

means for extracting features representative of timing delay of a first system-on-chip design and a second system-on-chip design;

means for applying a machine learning model to the extracted features to determine an error of the first system-on-chip design based on the second system-on-chip design; and

means for updating timing constraints of the second system-on-chip design based on the error determined for the first system-on-chip design.

16 . The apparatus of claim 15 , further including means for generating the machine learning model.

17 . The apparatus of claim 15 , further including means for optimizing the machine learning model.

18 . The apparatus of claim 15 , further including means for outputting a result of the machine learning model applied to the extracted features.

19 . A non-transitory machine readable storage medium comprising instructions that, when executed, cause processor circuitry to at least:

extract delay features from a first system-on-chip design and a second system-on-chip design;

apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design;

compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design; and

update timing constraints of the second system-on-chip design based on the error determined for the first system-on-chip design.

20 . The non-transitory machine readable storage medium of claim 19 , wherein the instructions further cause the processor circuitry to update the machine learning model based on the error determined of the first system-on-chip design.

21 . The non-transitory machine readable storage medium of claim 20 , wherein the instructions further cause the processor circuitry to modify a feature scale of the machine learning model.

22 . The non-transitory machine readable storage medium of claim 20 , wherein the instructions further cause the processor circuitry to modify a hyperparameter of the machine learning model.

23 . The non-transitory machine readable storage medium of claim 20 , wherein the instructions further cause the processor circuitry to remove a redundant feature from the machine learning model.

24 . The non-transitory machine readable storage medium of claim 20 , wherein the instructions further cause the processor circuitry to add a new feature to the machine learning model.

25 . The non-transitory machine readable storage medium of claim 19 , wherein the instructions further cause the processor circuitry to output the error determined of the first system-on-chip design.