Method of implementing an integrated circuit having a narrow-width cell and a wider-width cell with same functionality
View Patent ↗An integrated circuit includes a first circuit cell having a first width and a second circuit cell having a second width that is wider than the first width by at least one contacted poly pitch. An equivalent circuit of the first circuit cell is the same as an equivalent circuit of the second circuit cell.
1 . An integrated circuit, comprising:
a first circuit cell having a first width extending in a first direction;
a second circuit cell having a second width that is wider than the first width by at least one Contacted Poly Pitch (CPP), wherein an equivalent circuit of the first circuit cell is the same as an equivalent circuit of the second circuit cell;
a first connection pin and a second connection pin in a first metal layer and bounded between two vertical boundaries of the second circuit cell, wherein each of the first connection pin and the second connection pin has a length thereof extending in the first direction and a width thereof measured along a second direction, with the length larger than the width;
a first conducting line and a second conducting line, each of which extending in the second direction in a second metal layer above the first metal layer;
a first via connector directly connecting the first conducting line with the first connection pin;
a second via connector directly connecting the second conducting line with the second connection pin; and
a power grid line having a length thereof extending in the second direction in the second metal layer and passing across the second circuit cell, wherein the power grid line extends along the second direction between the first conducting line and the second conducting line.
2 . The integrated circuit of claim 1 , wherein the second width is larger than the first width by one CPP.
3 . The integrated circuit of claim 1 , wherein the second width is larger than the first width by two CPPs.
4 . The integrated circuit of claim 1 , wherein:
the first conducting line and the power grid line is separated by a pitch distance of one CPP; and
the second conducting line and the power grid line is separated by a pitch distance of one CPP.
5 . The integrated circuit of claim 1 , wherein:
the first conducting line and the power grid line is separated by a pitch distance of two thirds of one CPP; and
the second conducting line and the power grid line is separated by a pitch distance of two thirds of one CPP.
6 . The integrated circuit of claim 1 , wherein the equivalent circuit of the first circuit cell is the same as the equivalent circuit of the second circuit cell at a register-transfer level (RTL).
7 . The integrated circuit of claim 1 , further comprising:
a third connection pin and a fourth connection pin in the first circuit cell, each of which extending in the first direction, wherein a function of the third connection pin in the first equivalent circuit is the same as a function of the first connection pin in the second equivalent circuit, and wherein a function of the fourth connection pin in the first equivalent circuit is the same as a function of the second connection pin in the second equivalent circuit.
8 . The integrated circuit of claim 7 , further comprising:
a third conducting line and a fourth conducting line, each of which extending in the second direction;
a third via connector directly connecting the third conducting line with the third connection pin; and
a fourth via connector directly connecting the fourth conducting line with the fourth connection pin.
9 . The integrated circuit of claim 8 , wherein the third conducting line and the fourth conducting line are adjacent to each other.
10 . An integrated circuit, comprising:
a first circuit cell having a first width;
a second circuit cell having a second width that is wider than the first width by at least one Contacted Poly Pitch (CPP);
a first connection pin extending in a first direction in a first metal layer and bounded between two vertical boundaries of the second circuit cell, wherein the first connection pin has a length thereof extending in the first direction and a width thereof measured along a second direction, with the length larger than the width;
a first conducting line extending in the second direction in a second metal layer above the first metal layer and intersecting the first connection pin of the second circuit cell, the first direction being perpendicular to the first direction;
a power grid conducting line having a length thereof extending in the second direction in the second metal layer between the two vertical boundaries of the second circuit cell and passing across the second circuit cell, wherein the power grid conducting line is adjacent to and in parallel with the first conducting line; and
wherein the first circuit cell and the second circuit cell have same circuit functions.
11 . The integrated circuit of claim 10 , wherein the first circuit cell and the second circuit cell have a same equivalent circuit at a register-transfer level (RTL).
12 . The integrated circuit of claim 10 , wherein the first circuit cell and the second circuit cell have a same equivalent circuit as specified by a hardware description language.
13 . The integrated circuit of claim 10 , wherein the first circuit cell and the second circuit cell are different layout designs of a same logic gate.
14 . The integrated circuit of claim 10 , wherein the first circuit cell and the second circuit cell are different layout designs of different layout designs of a same analog circuit as described by a pre-layout netlist file.
15 . The integrated circuit of claim 10 , wherein the second width is larger than the first width by either one CPP or two CPPs.
16 . The integrated circuit of claim 10 , further comprising:
a second connection pin extending in the first direction in the second circuit cell; and
a second conducting line extending in the second direction and intersecting the second connection pin of the second circuit cell, wherein the power grid conducting line is also adjacent to the second conducting line.
17 . The integrated circuit of claim 10 , wherein the second width is larger than the first width by one CPP.
18 . A method comprising:
fabricating first-type active-region structures and second-type active-region structures, wherein each of first-type active-region structures and second-type active-region structures extends in a first direction;
fabricating gate-conductors and terminal-conductors extending in a second direction that is perpendicular to the first direction;
forming connection pins extending in the first direction in a first metal layer, wherein each of the connection pins has a length thereof extending in the first direction and a width thereof measured along the second direction, with the length larger than the width, wherein at least two connection pins are in a first circuit cell that has a first width and at least two connection pins are in a second circuit cell that has a second width, wherein the first circuit cell and the second circuit cell have same circuit functions, and wherein the second width is wider than the first width by at least one Contacted Poly Pitch (CPP);
fabricating via-connectors in one or more layers of interlayer dielectrics covering the connection pins; and
forming conducting lines extending in the second direction in a second metal layer overlying the interlayer dielectrics covering the connection pins, and wherein each of a first conducting line and a second conducting line is connected to, through one of the via-connectors, one of the connection pins which is bounded between two vertical boundaries of the second circuit cell; and
forming a power grid conducting line having a length thereof extending in the second direction in the second metal layer and passing across the second circuit cell, wherein the power conducting grid line extends along the second direction between the first conducting line and the second conducting line.
19 . The method comprising of claim 18 , wherein forming the connection pins comprises:
forming connection pins in a first metal layer overlying a first layer of interlayer dielectric covering the gate-conductors and terminal-conductors.
20 . The method comprising of claim 18 , wherein the forming conducting lines comprises:
forming a third conducting line and a fourth conducting line each of which connected to one of the connection pins in the first circuit cell through one of the via-connectors, wherein the third conducting line and the fourth conducting line are adjacent to each other.