IP Library › Granted Patent US 12699890
Granted Patent B2
US 12699890 · App. 18/520,277 · Granted Aug 4, 2026

Word line driver for vector-by-matrix multiplication array

Inventors: Hieu Van Tran (San Jose, CA); Stanley Hong (San Jose, CA); Anh Ly (San Jose, CA); Thuan Vu (San Jose, CA); Hien Pham (Ho Chi Minh, VN); Kha Nguyen (Ho Chi Minh, VN); Han Tran (Ho Chi Minh, VN)
Assignee: Silicon Storage Technology, Inc.
G06N3/065G06F17/16G06N3/04G11C11/54G11C16/0408
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12699890
App. No.
18/520,277
Granted
Aug 4, 2026
Kind
B2
Abstract

In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.

Claims (11)

1 . A system comprising:

a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns;

a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and

a word line driver coupled to the plurality of word lines, the word line driver comprising:

a plurality of select transistors, each of the plurality of select transistors comprising a first terminal, a second terminal, and a gate, wherein the gate of each of the plurality of select transistors is coupled to a common control line and the first terminal of each of the plurality of select transistors is coupled to a different word line, and wherein the second terminal of each of the plurality of select transistors is coupled to a first bias transistor to selectively provide to the select transistor a first voltage and a second bias transistor to selectively provide to the select transistor a second voltage lower than the first voltage;

wherein during a read or program operation, the common control line is asserted and one of the select transistors receives the first voltage from a first bias transistor and the other select transistors receive the second voltage from second bias transistors, each pair of first and second bias transistors controlled by different control lines; and

wherein during an analog neuromorphic read operation, the common control line is asserted and all of the select transistors receive the first voltage from first bias transistors.

2 . The system of claim 1 , wherein each of the first and second bias transistors is coupled to a circuit for decoding a word line address.

3 . The system of claim 1 , wherein each of the first and second bias transistors is coupled to a shift register.

4 . The system of claim 1 , wherein each of the first and second bias transistors is coupled to a capacitor.

5 . The system of claim 1 , wherein each of the first and second bias transistors is coupled to a comparator.