Application programming interface to check memory transaction information

Inventors: Harold Carter Edwards (Campbell, CA); Olivier Giroux (Santa Clara, CA); Jack H. Choquette (Palo Alto, CA); Gokul Ramaswamy Hirisave Chandra Shekhara (Bangalore, IN); Rui Guo (Shanghai, CN); Chao Li (Austin, TX); Vishalkumar Ketankumar Mehta (Stäfa, CH); David Dastous St. Hilaire (Lake Stevens, WA); Aditya Avinash Atluri (Redmond, WA); Apoorv Parle (San Jose, CA); Ronny Meir Krashinsky (Portola Valley, CA); Subhasmita Chakraborty (Austin, TX); Vikram Dhar (Campbell, CA)

Assignee: NVIDIA Corporation

G06T1/60 G06F3/061 G06F3/0625 G06F3/0659 G06F3/0673 G06F9/3004 G06F9/30087 G06F9/3877 G06F9/466 G06F9/467 G06F9/4881 G06F9/541 G06T1/20

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Quick Facts

Patent No.: US 12700056
App. No.: 18/081,550
Granted: Aug 4, 2026
Kind: B2

External Links

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Abstract

One or more processors include circuitry to, in response to an application programming interface (API) call, check for information provided in a token about one or more memory transactions after a first amount of time indicated by one or more input parameters of the API. A system includes one or more processors to, in response to an API call, check for information provided in a token about one or more memory transactions after a first amount of time indicated by one or more input parameters of the API. A method includes receiving an application programming interface (API) call and, in response to receiving the API call, checking for information provided in a token about one or more memory transactions after a first amount of time indicated by one or more input parameters of the API.

Claims (25)

1 . One or more processors, comprising:

circuitry to, in response to an application programming interface (API) call, check information provided in a token about one or more asynchronous memory transactions associated with a graphics processing unit (GPU) after a first amount of time indicated by one or more input parameters of the API, wherein, based on checking the information, the circuitry is to indicate that an expected state of a thread synchronization object provided in the token matches a current state of the thread synchronization object.

2 . The one or more processors of claim 1 , wherein the information includes the expected state of the thread synchronization object.

3 . The one or more processors of claim 1 , wherein the information includes the expected state of the thread synchronization object and the one or more asynchronous memory transactions are between a first memory of the GPU and a second memory of the GPU.

4 . The one or more processors of claim 1 , wherein the information includes a parity state of a barrier object and the one or more asynchronous memory transactions are between a first memory of the GPU and a second memory of the GPU.

5 . The one or more processors of claim 1 , wherein the API is to receive the token as an input.

6 . The one or more processors of claim 1 , wherein the API is to receive an identifier of the thread synchronization object as an input.

7 . The one or more processors of claim 1 , wherein the circuitry is to provide an indication of the current state of the thread synchronization object.

8 . A system, comprising:

one or more processors to, in response to an application programming interface (API) call, check information provided in a token about one or more asynchronous memory transactions associated with a graphics processing unit (GPU) after a first amount of time indicated by one or more input parameters of the API, wherein, based on checking the information, the one or more processors are to indicate that an expected state of a thread synchronization object provided in the token matches a current state of the thread synchronization object.

9 . The system of claim 8 , wherein the information includes the expected state of the thread synchronization object.

10 . The system of claim 8 , wherein the information includes the expected state of the thread synchronization object and the one or more asynchronous memory transactions are between a first memory of the GPU and a second memory of the GPU.

11 . The system of claim 8 , wherein the information includes a parity state of a barrier object and the one or more asynchronous memory transactions are between a first memory of the GPU and a second memory of the GPU.

12 . The system of claim 8 , wherein the API is to receive a pointer to the thread synchronization object as an input.

13 . The system of claim 8 , wherein the one or more processors are to provide an indication of the current state of the thread synchronization object.

14 . A method, comprising:

receiving an application programming interface (API) call;

in response to receiving the API call, checking information provided in a token about one or more asynchronous memory transactions associated with a graphics processing unit (GPU) after a first amount of time indicated by one or more input parameters of the API; and

outputting, based on checking the information, an indication that an expected state of a thread synchronization object provided in the token matches a current state of the thread synchronization object.

15 . The method of claim 14 , wherein the information includes the expected state of the thread synchronization object.

16 . The method of claim 14 , wherein the information includes the expected state of the thread synchronization object and the one or more asynchronous memory transactions are between a first memory of the GPU and a second memory of the GPU.

17 . The method of claim 14 , wherein the information includes a parity state of a barrier object and the one or more asynchronous memory transactions are between a first memory of the GPU and a second memory of the GPU.

18 . The method of claim 14 , wherein the API is to receive the token as an input.

19 . The method of claim 14 , wherein one or more processors are to provide an indication of the current state of the thread synchronization object.

20 . A non-transitory computer-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least perform the method of claim 14 .