Pixel circuit, display apparatus having the same, and an electronic device including the display device

1 . A pixel circuit comprising:

a first transistor comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;

a second transistor configured apply a data voltage to the first transistor;

a third transistor connected to the first node and the third node;

a fourth transistor configured to apply a first power voltage to the second node in response to a first emission signal;

a fifth transistor configured to apply a voltage of a fourth node to the third node in response to a second emission signal different from the first emission signal;

a sixth transistor configured to receive the first emission signal;

a seventh transistor configured to apply a driving current to a light emitting element and connected to the fourth node, the seventh transistor comprising a control electrode connected to the fourth node, a first electrode connected to a fifth node, and a second electrode directly connected to a first terminal of the light emitting element;

an eighth transistor comprising a control electrode configured to receive an initialization signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the first terminal of the light emitting element; and

a ninth transistor configured to apply an initialization voltage to the fourth node,

wherein the light emitting element is configured to emit light based on the driving current,

wherein the light emitting element initialization voltage is different from the initialization voltage,

wherein the initialization voltage has a low initialization voltage level or a constant current voltage level, and

wherein the first transistor is a P-type transistor, the second transistor is an N-type transistor, the third transistor is an N-type transistor, and the seventh transistor is a P-type transistor.

2 . The pixel circuit of claim 1 , wherein the ninth transistor comprises a control electrode configured to receive a scan signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the fourth node.

3 . The pixel circuit of claim 1 , further comprising a first capacitor comprising a first electrode configured to receive a sweep signal and a second electrode connected to the first node.

4 . The pixel circuit of claim 1 , wherein the sixth transistor comprises a control electrode configured to receive the first emission signal, a first electrode configured to receive a second power voltage, and a second electrode connected to the seventh transistor.

5 . The pixel circuit of claim 1 , further comprising a second capacitor including a first electrode receiving a second power voltage and a second electrode connected to the fourth node.

6 . The pixel circuit of claim 1 , wherein the second transistor comprises a control electrode configured to receive a first scan signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node, and

wherein the third transistor comprises a control electrode configured to receive the first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node.

7 . The pixel circuit of claim 1 , further comprising a first capacitor and a second capacitor,

wherein the second transistor comprises a control electrode configured to receive a first scan signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node,

wherein the third transistor comprises a control electrode configured to receive the first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node,

wherein the fourth transistor comprises a control electrode configured to receive the first emission signal, a first electrode configured to receive the first power voltage, and a second electrode connected to the second node,

wherein the fifth transistor comprises a control electrode configured to receive the second emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node,

wherein the sixth transistor comprises a control electrode configured to receive the first emission signal, a first electrode configured to receive a second power voltage, and a second electrode connected to the fifth node,

wherein the first electrode of the seventh transistor is configured to receive the second power voltage,

wherein the second electrode of the eighth transistor is connected to a sixth node connected to the first terminal of the light emitting element,

wherein the ninth transistor comprises a control electrode configured to receive a second scan signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the fourth node,

wherein the first capacitor comprises a first electrode configured to receive a sweep signal, and a second electrode connected to the first node,

wherein the second capacitor comprises a first electrode configured to receive the second power voltage and a second electrode connected to the fourth node, and

wherein the light emitting element comprises a first electrode connected to the sixth node and a second electrode configured to receive a third power voltage.

8 . The pixel circuit of claim 1 , further comprising a first capacitor and a second capacitor,

wherein the second transistor comprises a control electrode configured to receive a first scan signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node,

wherein the third transistor comprises a control electrode configured to receive the first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node,

wherein the fourth transistor comprises a control electrode configured to receive the first emission signal, a first electrode configured to receive the first power voltage, and a second electrode connected to the second node,

wherein the fifth transistor comprises a control electrode configured to receive the second emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node,

wherein the sixth transistor comprises a control electrode configured to receive the first emission signal, a first electrode configured to receive a second power voltage, and a second electrode connected to the fifth node,

wherein the second electrode of the seventh transistor is connected to a sixth node connected to the first terminal of the light emitting element,

wherein the second electrode of the eighth transistor is connected to the sixth node,

wherein the ninth transistor comprises a control electrode configured to receive a second scan signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the fourth node,

wherein the first capacitor comprises a first electrode configured to receive a sweep signal, and a second electrode connected to the first node,

wherein the second capacitor comprises a first electrode configured to receive the second power voltage and a second electrode connected to the fourth node, and wherein the light emitting element comprises a first electrode connected to the sixth node and a second electrode configured to receive a third power voltage.

9 . The pixel circuit of claim 8 , wherein the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are P-type transistors, and the ninth transistor is an N-type transistor.

10 . The pixel circuit of claim 8 , wherein the sixth transistor and the eighth transistor are P-type transistors, and the fourth transistor, the fifth transistor and the ninth transistor are N-type transistors.

11 . The pixel circuit of claim 8 , wherein the light emitting element initialization voltage is the third power voltage.

12 . The pixel circuit of claim 8 , wherein in a first period, the initialization voltage has the low initialization voltage level, the first scan signal has an activation level, the second scan signal has an activation level, the first emission signal has an inactivation level, the second emission signal has an activation level, and the initialization signal has an activation level, and

wherein in the first period, the third transistor, the fifth transistor, the eighth transistor and the ninth transistor are turned on, and the fourth transistor is turned off.

13 . The pixel circuit of claim 12 , wherein in a second period following to the first period, the initialization voltage has the low initialization voltage level, the first scan signal has an inactivation level, the second scan signal has an activation level, the first emission signal has an inactivation level, and the second emission signal has an inactivation level, and

wherein in the second period, the ninth transistor is turned on, and the fifth transistor is turned off.

14 . The pixel circuit of claim 13 , wherein in a third period following to the second period, the first scan signal has an activation level, and the second emission signal has an inactivation level, and

wherein in the third period, the second transistor and the third transistor are turned on, and the fifth transistor is turned off.

15 . The pixel circuit of claim 14 , wherein a fourth period following to the third period, the initialization voltage has the constant current voltage level, the second scan signal has an activation level, and the second emission signal has an inactivation level, and

wherein in the fourth period, the ninth transistor is turned on, and the fifth transistor is turned off.

16 . The pixel circuit of claim 15 , wherein a fifth period following to the fourth period, the sweep signal is gradually decreased from a high level, and the first emission signal has an activation level, and

wherein in the fifth period, the sixth transistor and the seventh transistor is turned on.

17 . The pixel circuit of claim 16 , wherein in a sixth period following to the fifth period, the sweep signal is gradually decreased, and the second emission signal has an activation level, and

wherein in the sixth period, the first transistor and the fifth transistor are turned on, and the seventh transistor is turned off.

18 . The pixel circuit of claim 17 , wherein in a seventh period following to the sixth period, the sweep signal has the high level, the first emission signal has an inactivation level, the second emission signal has an inactivation level, and the initialization signal has an activation level, and

wherein in the seventh period, the eighth transistor is turned on.

19 . A display apparatus comprising:

a display panel comprising a pixel circuit;

a gate driver configured to apply a gate signal to the pixel circuit;

an emission driver configured to apply an emission signal to the pixel circuit; and

a data driver configured to apply a data voltage to the pixel circuit,

wherein the pixel circuit comprises:

a first transistor comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;

a second transistor configured apply the data voltage to the first transistor;

a third transistor connected to the first node and the third node;

a fourth transistor configured to apply a first power voltage to the second node in response to a first emission signal;

a fifth transistor configured to apply a voltage of a fourth node to the third node in response to a second emission signal different from the first emission signal;

a sixth transistor configured to receive the first emission signal;

a seventh transistor configured to apply a driving current to a light emitting element and connected to the fourth node, the seventh transistor comprising a control electrode connected to the fourth node, a first electrode connected to a fifth node, and a second electrode directly connected to a first terminal of the light emitting element;

an eighth transistor comprising a control electrode configured to receive an initialization signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the first terminal of the light emitting element; and

a ninth transistor configured to apply an initialization voltage to the fourth node,

wherein the light emitting element configured to emit light based on the driving current,

wherein the light emitting element initialization voltage is different from the initialization voltage,

wherein the initialization voltage has a low initialization voltage level or a constant current voltage level, and

wherein the first transistor is a P-type transistor, the second transistor is an N-type transistor, the third transistor is an N-type transistor, and the seventh transistor is a P-type transistor.

20 . An electronic device comprising a display device, the display device comprising:

a display panel comprising a pixel circuit; and

a display driver configured to drive the display panel,

wherein the pixel circuit comprises:

a first transistor comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;

a second transistor configured apply a data voltage to the first transistor;

a third transistor connected to the first node and the third node;

a fourth transistor configured to apply a first power voltage to the second node in response to a first emission signal;

a fifth transistor configured to apply a voltage of a fourth node to the third node in response to a second emission signal different from the first emission signal;

a sixth transistor configured to receive the first emission signal;

a seventh transistor configured to apply a driving current to a light emitting element and connected to the fourth node, the seventh transistor comprising a control electrode connected to the fourth node, a first electrode connected to a fifth node, and a second electrode directly connected to a first terminal of the light emitting element;

an eighth transistor comprising a control electrode configured to receive an initialization signal, a first electrode configured to receive a light emitting element initialization voltage, and a second electrode connected to the first terminal of the light emitting element; and

a ninth transistor configured to apply an initialization voltage to the fourth node,

wherein the light emitting element is configured to emit light based on the driving current,

wherein the light emitting element initialization voltage is different from the initialization voltage,

wherein the initialization voltage has a low initialization voltage level or a constant current voltage level, and

wherein the first transistor is a P-type transistor, the second transistor is an N-type transistor, the third transistor is an N-type transistor, and the seventh transistor is a P-type transistor.

21 . The electronic device of claim 20 , wherein the electronic device comprises a cellular phone, a video phone, a smart pad, a television (TV), smart watch, a car navigation system, a computer monitor, a laptop, or a head mounted display (HMD) device.