IP Library › Granted Patent US 12700355
Granted Patent B2
US 12700355 · App. 19/340,933 · Granted Aug 4, 2026

Light emitting signal generation circuit and shift register

Inventors: Che-Chia Chang (Hsinchu City, TW); Che-Wei Tung (Hsinchu City, TW); Mei-Yi Li (Hsinchu City, TW); Yu-Chieh Kuo (Hsinchu City, TW); Yu-Hsun Chiu (Hsinchu City, TW); En-Chih Liu (Hsinchu City, TW); Ming-Hung Chuang (Hsinchu City, TW)
Assignee: AUO CORPORATION
G09G3/32G09G2300/0426G09G2300/0842G09G2310/0286G09G2310/08
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Quick Facts
Patent No.
US 12700355
App. No.
19/340,933
Granted
Aug 4, 2026
Kind
B2
Abstract

A light emitting signal generation circuit is provided and configured to drive a pixel column in a pixel array and includes first, second, and third circuit units. The first circuit unit generates a global light emitting signal based on total clock signals, first and second reference signals. The second circuit unit is coupled to the first circuit unit and generates a first light emitting signal based on the global light emitting signal, the first and second reference signals, and a first clock signal. The first light emitting signal drives first and third sub-pixels of the pixel column. The third circuit unit is coupled to the first circuit unit and generates a second light emitting signal based on the global light emitting signal, the first and second reference signals, and a second clock signal. The second light emitting signal drives a second sub-pixel of the pixel column.

Claims (67)

1 . A light emitting signal generation circuit for driving a pixel column in a pixel array, comprising:

a first circuit unit, configured to generate a global light emitting signal based on a plurality of global clock signals, a first reference signal, and a second reference signal;

a second circuit unit, coupled to the first circuit unit, and configured to generate a first light emitting signal based on the global light emitting signal, the first reference signal, the second reference signal, and a first clock signal, wherein the first light emitting signal is configured to drive a first sub-pixel of the pixel column; and

a third circuit unit, coupled to the first circuit unit, and configured to generate a second light emitting signal based on the global light emitting signal, the first reference signal, the second reference signal, and a second clock signal, wherein the second light emitting signal is configured to drive a second sub-pixel of the pixel column; and

a fourth circuit unit, coupled to the first circuit unit, and configured to generate a third light emitting signal based on the global light emitting signal, the first reference signal, the second reference signal, and a third clock signal, wherein the third light emitting signal is configured to drive a third sub-pixel of the pixel column.

2 . The light emitting signal generation circuit of claim 1 , wherein the first circuit unit further comprises:

a coupling circuit, configured as an output stage of the first circuit unit and configured to transmit the first reference signal and the second reference signal to the second circuit unit, the third circuit unit, and the fourth circuit unit.

3 . The light emitting signal generation circuit of claim 2 , wherein the second circuit unit, the third circuit unit and the fourth circuit unit are coupled to a first node of the coupling circuit, the coupling circuit comprises:

a first transistor, a first terminal of the first transistor receives the first reference signal, and a second terminal of the first transistor is coupled to the first node, wherein the first transistor is turned on to transmit the first reference signal to the first node; and

a second transistor, a first terminal of the second transistor is coupled to the first node, and a second terminal of the second transistor receives the second reference signal, wherein the second transistor is turned on to transmit the second reference signal to the first node.

4 . The light emitting signal generation circuit of claim 3 , wherein the second circuit unit comprises:

a third transistor, wherein a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives the first reference signal;

a fourth transistor, wherein a first terminal of the fourth transistor receives the first clock signal, and a control terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a second terminal of the fifth transistor receives the second reference signal, and a control terminal of the fifth transistor is coupled to a control terminal of the second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the capacitor is coupled to the first terminal of the fifth transistor and is configured to output the first light emitting signal.

5 . The light emitting signal generation circuit of claim 3 , wherein the third circuit unit comprises:

a third transistor, wherein a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives the first reference signal;

a fourth transistor, wherein a first terminal of the fourth transistor receives the second clock signal, and a control terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a second terminal of the fifth transistor receives the second reference signal, and a control terminal of the fifth transistor is coupled to a control terminal of the second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the capacitor is coupled to the first terminal of the fifth transistor and is configured to output the second light emitting signal.

6 . The light emitting signal generation circuit of claim 3 , wherein the fourth circuit unit comprises:

a third transistor, wherein a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives the first reference signal;

a fourth transistor, wherein a first terminal of the fourth transistor receives the third clock signal, and a control terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a second terminal of the fifth transistor receives the second reference signal, and a control terminal of the fifth transistor is coupled to a control terminal of the second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the capacitor is coupled to the first terminal of the fifth transistor and is configured to output the third light emitting signal.

7 . The light emitting signal generation circuit of claim 1 , wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

8 . A light emitting signal generation circuit for driving a pixel column in a pixel array, comprising:

a first circuit unit configured to generate a global light emitting signal based on a plurality of global clock signals, a first reference signal, and a second reference signal;

a second circuit unit coupled to the first circuit unit and configured to generate a first light emitting signal based on the global light emitting signal, the first reference signal, the second reference signal, and a first clock signal, wherein the first light emitting signal is configured to drive a first sub-pixel and a third sub-pixel of the pixel column; and

a third circuit unit coupled to the first circuit unit, and configured to generate a second light emitting signal based on the global light emitting signal, the first reference signal, the second reference signal, and a second clock signal, wherein the second light emitting signal is configured to drive a second sub-pixel of the pixel column.

9 . The light emitting signal generation circuit of claim 8 , wherein the first circuit unit further comprises:

a coupling circuit configured as an output stage of the first circuit unit and configured to transmit the first reference signal and the second reference signal to the second circuit unit and the third circuit unit.

10 . The light emitting signal generation circuit of claim 9 , wherein the second circuit unit and the third circuit unit are coupled to a first node of the coupling circuit, the coupling circuit comprises:

a first transistor, wherein a first terminal of the first transistor receives the first reference signal, and a second terminal of the first transistor is coupled to the first node, wherein the first transistor is turned on to transmit the first reference signal to the first node; and

a second transistor, wherein a first terminal of the second transistor is coupled to the first node, and a second terminal of the second transistor receives the second reference signal, wherein the second transistor is turned on to transmit the second reference signal to the first node.

11 . The light emitting signal generation circuit of claim 10 , wherein the second circuit unit comprises:

a third transistor, wherein a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives the first reference signal;

a fourth transistor, wherein a first terminal of the fourth transistor receives the first clock signal, and a control terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a second terminal of the fifth transistor receives the second reference signal, and a control terminal of the fifth transistor is coupled to a control terminal of the second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the capacitor is coupled to the first terminal of the fifth transistor and is configured to output the first light emitting signal.

12 . The light emitting signal generation circuit of claim 10 , wherein the third circuit unit comprises:

a third transistor, wherein a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives the first reference signal;

a fourth transistor, wherein a first terminal of the fourth transistor receives the second clock signal, and a control terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a second terminal of the fifth transistor receives the second reference signal, and a control terminal of the fifth transistor is coupled to a control terminal of the second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the capacitor is coupled to the first terminal of the fifth transistor and is configured to output the second light emitting signal.

13 . The light emitting signal generation circuit of claim 8 , wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

14 . A shift register, comprising:

a plurality of light emitting signal generation circuits for each generating and sequentially transmitting a global light emitting signal to sequentially drive a plurality of pixel columns in a pixel array, and each of the light emitting signal generation circuits comprises:

a first circuit unit configured to generate the global light emitting signal based on a plurality of global clock signals, a first reference signal, and a second reference signal;

a second circuit unit coupled to the first circuit unit and configured to generate a first light emitting signal based on the global light emitting signal, the first reference signal, the second reference signal, and a first clock signal, wherein the first light emitting signal is configured to drive a first sub-pixel and a third sub-pixel of a corresponding one of the pixel columns; and

a third circuit unit coupled to the first circuit unit and configured to generate a second light emitting signal based on the global light emitting signal, the first reference signal, the second reference signal, and a second clock signal, wherein the second light emitting signal is configured to drive a second sub-pixel of the corresponding one of the pixel columns.

15 . The shift register of claim 14 , wherein the first circuit unit further comprises:

a coupling circuit, configured as an output stage of the first circuit unit and configured to transmit the first reference signal and the second reference signal to the second circuit unit and the third circuit unit.

16 . The shift register of claim 15 , wherein the second circuit unit and the third circuit unit are coupled to a first node of the coupling circuit, the coupling circuit comprises:

a first transistor, wherein a first terminal of the first transistor receives the first reference signal, and a second terminal of the first transistor is coupled to the first node, wherein the first transistor is turned on to transmit the first reference signal to the first node; and

a second transistor, wherein a first terminal of the second transistor is coupled to the first node, and a second terminal of the second transistor receives the second reference signal, wherein the second transistor is turned on to transmit the second reference signal to the first node.

17 . The shift register of claim 16 , wherein the second circuit unit comprises:

a third transistor, wherein a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives the first reference signal;

a fourth transistor, wherein a first terminal of the fourth transistor receives the first clock signal, and a control terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a second terminal of the fifth transistor receives the second reference signal, and a control terminal of the fifth transistor is coupled to a control terminal of the second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the capacitor is coupled to the first terminal of the fifth transistor and is configured to output the first light emitting signal.

18 . The shift register of claim 16 , wherein the second circuit unit comprises:

a third transistor, wherein a first terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives the first reference signal;

a fourth transistor, wherein a first terminal of the fourth transistor receives the second clock signal, and a control terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a second terminal of the fifth transistor receives the second reference signal, and a control terminal of the fifth transistor is coupled to a control terminal of the second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the capacitor is coupled to the first terminal of the fifth transistor and is configured to output the second light emitting signal.

19 . The shift register of claim 14 , wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.